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ALgorithm parallelization
for Multicore Architectures
Faster time-to-market for embedded multicore
systems with less application development effort
Application Test Case
FEATURES
IEEE 802.16e PHY Layer in NT x NR MIMO
Configuration
 State-of-the-art WiMAX wireless communication

Develop algorithms
and tools to:
Scilab Input Language
ALMA subset of the Scilab language
 Extended by
 Variables declaration
 Static types specification
 Maximum size of vector/matrix data type
definition
Automatic
parallelization of
high-level Scilab
algorithms to
embedded
MPSoCs

Matrix Frontend (MFE)
Hide hardware
complexity from the
software developer
Translate Scilab intermediate representation
 Generates static C code optimized for
parallelization
 Constant and data type propagation

Iterative Optimization
Provide
target-agnostic
parallelization tools
Simulation and Performance Analysis
of intermediate results
 Performance metric feedback-loop

Iterative
performance
estimation and
optimizations
RESULTS
Automatic
conversion from
Scilab to embedded
C Code
Automatic
parallelization to 4
processing cores
Minimization of
sequential code
Equal Workload
distribution
x2.4 application
speedup
ALMA
www.alma-project.eu
Coordinator
Jürgen Becker (KIT)
Contact
[email protected]
Budget
3.200.000 €
Start Date
01/09/2011
Duration
41 Months
Algorithm Parallelization
Fine-grain parallelization
 Loop optimization
 Floating- to fixed Point conversion
 SIMD/SWP vectorization
 Coarse-grain parallelization
 Increases available CG parallelism
 Use hierarchical task graphs
 Parallel task mapping and scheduling

Architecture Description
Enables target independence of the
toolchain
 Structural specification annotated
with behavioural information

Parallel Code Generation
Map Scilab variables to memory
locations
 Insert and optimize communication
 Generates target-specific MPI-like C
code

This work is co-funded by the European Union under the 7th Framework Programme under grant agreement ICT-287733.