1. Ingeniería

Distributed Power Amplifiers for Software
Defined Radio Applications
Von der Fakultät für Elektrotechnik und Informationstechnik
der Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines
Doktors der Ingenieurwissenschaften
genehmigte Dissertation
vorgelegt von
Narendra Kumar, M.Sc B.E(Hons)
aus Penang, Malaysia
Berichter:
Univ.-Prof. Dr.-Ing. Rolf H. Jansen
Univ.-Prof. Dr.-Ing. Dirk Heberling
Univ.-Prof. Ernesto Limiti
Tag der mündlichen Prüfung: 23. Mai 2011
Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar
i
Acknowledgements
I would not be able to complete this thesis without the support of numerous individuals and institutions
e.g. Prof. Dr.-Ing. Rolf H. Jansen (RWTH Aachen University, Germany), Bob Stengel (Motorola Labs,
Florida, US), Chacko Prakash (Motorola Research Center, Malaysia), Prof. Ernesto Limiti (University
Roma Tor Vergata, Italy), Prof. Claudio Paoloni (University Roma Tor Vergata, Italy), Prof. Juan-Mari
Collantes (University of Basque Country, Spain), Prof. Yarman Siddik (Istanbul University, Turkey),
Thomas Chong ((Motorola Research Center, Malaysia), Dr. Vitaliy Zhurbenkho (Technical University
Denmark, Denmark).
I would like to express my special gratitude to Prof. Dr.-Ing. Rolf H. Jansen, the head of the Chair of
Electromagnetic Theory (ITHE), RWTH Aachen University, for giving me the opportunity and the freedom
to complete my Ph.D research under his supervision. Also, I would like to thank him for supporting me
with the insight in academic aspects and the fruitful discussions. I am grateful to Prof. Dr.-Ing.
Dirk Heberling to be co-referee and Prof. Ernesto Limiti as an external examiner for my thesis
examination.
In addition, I am grateful to Motorola Education Assistance Board (Lee SiewYin, Fam FookTeng, Dr. Hari
Narayan, Chacko Prakash, and the team) for providing financial support. Special thank to Prof. Claudio
Paoloni for his help in reviewing my thesis and provide comments. Also, sincere gratitude to Fam
FookTeng, Chacko Prakash and Joey Ooi (Motorola Research Center, Florida, US) for their
encouragement and motivation given during my work.
My sincere gratitude extends to my parents, beloved wife and all my colleagues and friends for their kind
assistance and support, including Aridas, Indra, Sangeran, Banu, Phuvaneswary, Pragash, Lokesh,
Maisarah, Sathish Arumugam, Jesus Cumana, Jens Goliasch, Christian Lautensack, Sun Golian, Koh
BoonPing, Solomon Lorthu, Macwien Krishnamurthy, Mohd. Fadli, Joshua Lee, Tan TiekSiew, Prabakar,
Mahadev, Kogilavani, Megalah, Yogeswaran, Jeevan Kanesan, Harikrishnan, Ramesh Kumar, Shankar
Karuppayah and Loganathan.
ii
Contents
List of Acronyms and Symbols …………………………………………………………………………………vi
List of Figures ….………………………………………………………………. …………………………………ix
List of Tables ….………………………………………………………………. …………………………………xvi
1
2
3
Introduction ......................................................................................................................................... 1
1.1
Objective of This Work ............................................................................................................ 1
1.2
Thesis Organization ................................................................................................................ 2
Broadband Amplifier Limitations and Designs................................................................................ 3
2.1
Bandwidth Limitation Analysis................................................................................................. 3
2.2
Broadband switched-mode amplifier ....................................................................................... 5
2.2.1
Parallel-circuit class E with reactance compensation technique ............................................ 5
2.2.2
Excessive capacitance absorption with shunt C-LC network ................................................. 7
2.3
Broadband High Linearity and Efficient amplifier .................................................................. 10
2.4
Multi-stage broadband amplifier ............................................................................................ 11
2.5
Balanced amplifier (BA) ........................................................................................................ 12
2.6
Unified Broadband Matching Approach ................................................................................ 14
2.7
Conclusion............................................................................................................................. 15
Distributed Amplification Concept and Practical Distributed Amplifiers Design methodology ..
............................................................................................................................................................ 16
3.1
3.1.1
Introduction............................................................................................................................ 16
3.1.2
Image impedance method..................................................................................................... 18
3.2
4
Concept of Distributed Amplification ..................................................................................... 16
Theoretical Analysis of DA .................................................................................................... 20
3.2.1
Analytical approach of Beyer model (Two-port theory) ......................................................... 21
3.2.2
Analytical approach of Niclas model (Admittance matrix) ..................................................... 23
3.2.3
Analytical approach of McKay model (Wave theory) ............................................................ 25
3.3
Gain/ Power-bandwidth trade-off .......................................................................................... 27
3.4
Design Methodology of Practical DA .................................................................................... 31
3.5
Conclusion............................................................................................................................. 39
Efficiency Analysis in Distributed Amplifier .................................................................................. 40
4.1
Efficiency Limitations in DA ................................................................................................... 40
4.2
Virtual Impedance analysis due to multi current sources ..................................................... 41
4.3
High Efficiency DA Development .......................................................................................... 50
4.3.1
Simulation Analysis ............................................................................................................... 50
4.3.2
Design Example of High Efficiency DA ................................................................................. 52
iii
4.3.3
Broadband Impedance Transformer Design ......................................................................... 56
4.3.4
Measurement Results ........................................................................................................... 61
4.4
4.4.1
Motivation .............................................................................................................................. 64
4.4.2
Principle Operation ................................................................................................................ 64
4.4.3
Design Example of DFDA with termination adjustment ........................................................ 69
4.4.4
Measurement Results ........................................................................................................... 73
4.5
5
Conclusion............................................................................................................................. 75
Stability Analysis in Distributed Amplifiers ................................................................................... 76
5.1
Motivation of Stability Analysis .............................................................................................. 76
5.2
Stability Analysis Methods .................................................................................................... 77
5.2.1
K-factor stability of a two port network .................................................................................. 77
5.2.2
Feedback and NDF factor ..................................................................................................... 79
5.2.3
Pole-zero identification method ............................................................................................. 82
5.3
Analysis and Conditions of Stability in DAs .......................................................................... 83
5.4
Parametric oscillations detection in DAs ............................................................................... 91
5.4.1
Introduction............................................................................................................................ 91
5.4.2
Stability Analysis of DA ......................................................................................................... 91
5.4.3
Circuit Stabilization and Measurement Results .................................................................... 93
5.5
6
Dual Fed DA with Termination Adjustment ........................................................................... 64
Conclusion............................................................................................................................. 96
Distributed Power Amplifiers for SDR Applications ..................................................................... 97
6.1
First DPA development ......................................................................................................... 97
6.1.1
Motivation .............................................................................................................................. 97
6.1.2
Circuit Analysis ...................................................................................................................... 99
6.1.3
Stability Analysis ................................................................................................................. 106
6.1.4
Design and Measurement Prototype .................................................................................. 108
A. Objective ...................................................................................................................................... 108
B. Design Example and Layout Considerations .............................................................................. 108
C. Measurement Results ................................................................................................................. 112
6.2
Second DPA development .................................................................................................. 114
6.2.1
Motivation ............................................................................................................................ 114
6.2.2
Concept of Vectorially combined current sources with load pull determination.................. 116
6.2.3
Design and Measurement Prototype .................................................................................. 118
A. Objective ...................................................................................................................................... 118
B. Design Example and Layout Considerations .............................................................................. 118
iv
C. Measurement Results ................................................................................................................ 124
6.2.4
6.3
7
Real-Frequency Broadband Transformer/Filter .................................................................. 128
Conclusion........................................................................................................................... 140
Conclusion and Future Work ......................................................................................................... 141
7.1
Conclusion........................................................................................................................... 141
7.2
Future Work ……………………………………………………………………………………….142
7.2.1
Output loading compensation for GaN DPA ....................................................................... 142
A. Theoretical Analysis ..................................................................................................................... 142
B. Design Example ........................................................................................................................... 145
Appendix A: Layout Guidelines ............................................................................................................ 148
Biblography ............................................................................................................................................. 154
Curriculum Vitae ………………………………………………………………………………………………...162
v
List of Acronyms and Symbols
Acronyms:
ACPR
Adjacent channel power ratio
ADS
Advanced design system
BA
Balanced amplifier
CST
Computer simulation technology
DA
Distributed amplifier
DC
Direct current
DFDA
Dual fed distributed amplifier
DPA
Distributed power amplifier
DPQSK
Digital phase quadrate shift keying
EM
Electro magnetic
FET
Field effect transistor
GaAs
Gallium arsenide
GaN
Gallium nitride
HB
Harmonic balance
HBT
Hetero-junction bipolar transistor
HEMT
High electron mobility transistor
JTRS
Joint Tactical Radio System
LDMOS
Lateral diffusion MOS
LNA
Low noise amplifier
MMIC
Monolithic microwave integrated circuit
MOSFET
Metal oxide semiconductor field effect transistor
NDF
Normalized determinant function
PA
Power amplifier
PAE
power aided efficiency
PCB
Printed circuit board
PBW
Power bandwidth product
PSK
Phase shift keying
RFT
Real frequency technique
RF-DCT
Real frequency - Direct computational technique
RF-LST
Real frequency - Line segment technique
SiC
Silicon Carbide
SDR
Software defined radios
TDMA
Time division multiple access
TETRA
Trans-European trunked radio
vi
TPG
Transducer power gain
UHF
Ultra high frequency
VCCS
Voltage controlled current source
VCO
Voltage controlled oscillator
VHF
Very high frequency
Symbols:
AB
loop gain
C
Capacitance
θg
Gate line propagation delay
θd
Drain line propagation delay
Cds
Drain to source capacitance
Cgd
Gate to drain capacitance
Cgs
Gate to source capacitance
Vbk
Breakdown voltage
Id
Drain voltage
BW
Bandwidth
Vk
Knee voltage
RL
Load impedance
RL,opt
Optimum lad impedance
Pout
Output power
IDSS
Saturation current
gm
Trans-conductance
fτ
Transition frequency
Q
Quality factor
G
Conductance
R
Resistance
L
Inductance
Vgs
Voltage across Cgs
Y
Admitance
Z
Impedance
ZOT
Characteristic impedance of the T-section network
Z Oπ
Characteristic impedance of the π-section network
fc
Center frequency
Rds
Drain to source resistive
Rgs
Gate to source resistive
αg
Gate line attenuation
vii
αd
Drain line attenuation
ωg
Gate line corner frequency
ωd
Drain line corner frequency
nopt
Optimum number of section
RFin
Input RF drive
RFout
Output RF power
Γin
Input reflection coefficient
Γout
Output reflection coefficient
RR
Feedback factor
H(jω)
Transfer function in frequency response
ZB(p)
Minimum function
ZF(p)
Foster function
ε(ω)
Error function
F
Feedback factor
γij
Immitance of i,j elements
Rgen
Generator impedance
Zu(k)
Impedance seen by current source in upper direction
Zr(k)
Impedance seen by current source in right direction
vin
Input voltage
vout
Output voltage
viii
List of Figures
Figure 2.1: Equivalent network of the input port under conjugate matched conditions. ................................................. 4
Figure 2.2: Basic diagram of load network of parallel-circuit class E power amplfiers. .................................................. 5 Figure 2.3: Reactance compensation principle using series and parallel resonant circuits. .......................................... 6 Figure 2.4: Photograph of prototype board of broadband parallel-circuit class E PA with reactance compensation. .... 7 Figure 2.5: Broadband class E amplifier with shunt C-LC network providing constant load angle and absorbing
excessive capacitance in the device. ............................................................................................................................ 8 Figure 2.6: The load output network is designed to show ideal impedance to the switch for the complete broadband
(400-470MHz) in this example....................................................................................................................................... 9 Figure 2.7: Photograph of prototype of broadband shunt C-LC class E UHF PA. ......................................................... 9 Figure 2.8: Block diagram of adaptive bias technique. ................................................................................................ 10 Figure 2.9: Test board of the broadband high linearity and efficiency PA employing Cartesian feedback. ................. 11 Figure 2.10: Photograph of prototype board of broadband parallel-circuit Class E PA with reactance compensation
technique. .................................................................................................................................................................... 12 Figure 2.11: Basic BA configuration. ............................................................................................................................ 13 Figure 2.12: Photograph of prototype board of BA. ..................................................................................................... 13 Figure 2.13: Ideal form of the transducer power gain over the specified frequency bandwidth. .................................. 14 Figure 2.14: Typical diagram illustrating filter or insertion loss problem. ..................................................................... 15 Figure 2.15: Darlington equivalent of a driving point impedance Z or reflection S. ...................................................... 15 Figure 3.1: Basic topology of DA. Lg and Ld are denote gate and drain line, respectively. Vin is the input signal feeding,
and Vout is output voltage [28]. ..................................................................................................................................... 16 Figure 3.2: The distributed amplification concept. ....................................................................................................... 17 Figure 3.3: Lossless elementary section of DA a) gate line b) drain line. .................................................................... 18 Figure 3.4: A two-port network. ................................................................................................................................... 18 Figure 3.5: A two-port network terminated by its image impedance. ........................................................................... 19 Figure 3.6: Artificial transmission line. ......................................................................................................................... 19 Figure 3.7: A low pass L section by means of constant-k image impedance............................................................... 20 Figure 3.8: Simplified small signal circuit model of a transistor. .................................................................................. 21 Figure 3.9: (a) Gate transmission line and b) drain transmission line. ......................................................................... 23 Figure 3.10: Equivalent four-port representation of the circuit of DA form [6]. ............................................................. 24 Figure 3.11: Elementary section of bilateral distributed amplifier. The variables bn and an represent scattering waves
[29]. ............................................................................................................................................................................. 26 Figure 3.12: A simple bandpass amplifier schematic. ................................................................................................. 27 Figure 3.13: Normalized gain over frequency response for various selection of a, b and n = 4…………………………29 Figure 3.14:Maximum transistor output is given by Gp⋅Pin(max) for non-uniform DA. ..................................................... 30 Figure 3.15: Connecting few stages of non-identical transistors with inter-stage tapered impedance (broadband
matching networks e.g. M1,..,M2) can increase Pin(max) to the power transistor, and having high-fτ transistor (lowest
Cgs) can be coupled to the gate line input. Q1,..,QN are high-fτ transistors. ................................................................. 30 Figure 3.16: αg (red color) and αd (blue color) of the GaN power transistor. The αg and αd of the transistor are
computed from the intrinsic elements, Table 3.1. ........................................................................................................ 31 ix
Figure 3.17: Break-down voltage Vbk vs. output power Pout for 50 Ω condition. ........................................................... 33 Figure 3.18: Simplified small-signal FET model. ......................................................................................................... 33
Figure 3.19: VCCS and Cgd of a single DA. Other intrinsic elements are included in the VCCS section ..................... 33
Figure 3.20: Basic FET DC bias arrangement. ............................................................................................................ 34 Figure 3.21: Broadband choke implementation given in [84]. ...................................................................................... 34 Figure 3.22: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω . Z0i, i = 1, 2..n,
referring to line impedance; consists of shunt capacitance and inductance. Note that dummy termination is neglected
to push all current to the load ZL. ................................................................................................................................. 35 Figure 3.23: S11 of a common emitter medium power device in packaged and die form [36]. ..................................... 35 Figure 3.24: (a) Properties of high power GaN packaged device (CGH40010F) [85], and (b) illustration of optimum
load impedance Ropt’ (at reference A) and Ropt (at reference B). ................................................................................. 36 Figure 3.25: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω . Note that dummy
termination is neglected to push all current to the load RL. i denotes 1, 2..n ............................................................... 37 Figure 3.26: Differential via-hole study to understand coupling effect for optimum grounding potential, especially at
higher frequency. ......................................................................................................................................................... 37 Figure 3.27: Cross-sectional diagram of high power GaN amplifier and PCB. ............................................................ 38 Figure 4.1: Impedance Zπ seen by each transistor in both directions, of half right and half left. .................................. 41 Figure 4.2: Two current sources are combining at a single node. ............................................................................... 42 Figure 4.3: Simplification of circuit from Figure 4.2 to understand Z1. ......................................................................... 43 Figure 4.4: The plot of real and imaginary Z1/R vs. (θ2-θ1) for few cases I2/I1 from (4.8). ............................................ 44 Figure 4.5: The virtual impedance, Zi seen by the current generator in two directions (Zu(k) and Zr(k)), respectively and
k = 1, 2, 3 .. n. ............................................................................................................................................................. 44 Figure 4.6: Simplification network of current generator, i1 and Norton equivalent network of Figure 4.5 to determine
Zu(1). ............................................................................................................................................................................. 45 Figure 4.7: Real and imaginary Zu(k)/R (k = 1,2, 3 and 4) vs. (θa - θb) for identical current sources, I1 = I2 = I3 = I4. The
response Zu(1)/R = Zu(2)/R = Zu(3)/R = Zu(4)/R. ............................................................................................................... 47 Figure 4.8: Real and imaginary Zr(k)/R (k = 1, 2, 3 and 4) vs. (θa - θb) for identical current sources, I1 = I2 = I3 = I4. For
k=4, the imaginary part is null. ..................................................................................................................................... 47 Figure 4.9: Zr(k) is evaluated according to (4.20) – (4.23), to design artificial transmission. The output capacitance
parallel to the current source typically known Cds will be absorbed in the artificial transmission line design. .............. 49 Figure 4.10: Input gate line coupled with external capacitor in series with Cgs. Note that the elements may have
different values if unequal injection is required. ........................................................................................................... 49 Figure 4.11: Circuit showing multi-current sources to combine at a single load termination, R = 50 Ω. ...................... 50 Figure 4.12: Vector diagram of magnitude and phase of the current properties for the Figure 4.11, where magnitude
and phase of the current sources are equal. i1 is set to be reference. ......................................................................... 51 Figure 4.13: Power delivered by each current source with matched delay values connected to output transmission
line. Note all the sources deliver maximum power and having the same energy level over the frequency range. ...... 51 Figure 4.14: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω load termination. All
the current sources loaded with parallel resistor of 1 MΩ. ........................................................................................... 52 Figure 4.15: Power delivered by each ideal current source non-uniform drain line with lumped elements. Note the
st
nd
rd
th
graph colors (red is 1 source, blue is 2 source, yellow is 3 source and green is 4 source, respectively). ........... 52 Figure 4.16: Simplified 4-section DA applying non-uniform drain line impedance. m-derived section is implemented
close to termination of gate line. .................................................................................................................................. 53 Figure 4.17: Simulated analysis of S11 and S22 for various load terminations, R for circuit shown in Figure 4.16. The
color: green is for R of 5 Ω, brown curve is 8 Ω, blue curve is 12.5 Ω, red curve is 25 Ω and orange curve is 50 Ω. .. 54 x
Figure 4,18: Simulated analysis of PAE and gain for various load terminations R for circuit shown in Figure 4.16. The
color: green is for R of 5 Ω, brown curve is 8 Ω, blue curve is 12.5 Ω, red curve is 25 Ω and orange curve is 50 Ω. .. 55 Figure 4,19: Magnitude of load current for of non-uniform (red curve) and uniform (blue curve) gate line design across
the frequency range (10 – 1800 MHz). ........................................................................................................................ 55 Figure 4.20: General coupled line configuration. The four-port section is reduced to a two-port with coupled and
through ports can be loaded with an external impedance termination [118]. In this figure, through port is terminated
with termination impedance Z4. ................................................................................................................................... 56 Figure 4.21: Two-port network representation for the coupled line transformer [118]. ................................................ 57 Figure 4.22: Proposal circuit of the compact impedance transformer, and the impedance transformation from 12.5 Ω
to 50 Ω......................................................................................................................................................................... 57 Figure 4.23: Analysis result of output return loss S22 response of the 12.5-50 Ω impedance transformer shown in
Figure 4.24. 6 zero (minima) reflections exist across the frequency range. For comparison, the transformer shown in
[118] is included. ......................................................................................................................................................... 58 Figure 4.24: a) Layout structure of the transformer imported from Cadence and the simulation is performed in CST (b)
actual prototype board. ................................................................................................................................................ 59 Figure 4.25: (a) Connector modeling in CST, where waveguide and lumped ports are used, and (b) Simulated (red
curve) and measured results (blue curve) of the connector across the bandwidth. ..................................................... 59 Figure 4.26: Simulated vs. measured results of insertion loss S21 of the transformer. Simulation response of the
broadband impedance transformer is performed with CST (line with triangle and blue curve) and measured result is
referred to red line with curve. ..................................................................................................................................... 60 Figure 4.27: Simulated vs. measured results of output return loss S22 of the transformer. Simulation response of the
broadband impedance transformer is performed with CST (line with triangle and blue curve) and measured result is
referred to red line with curve. ..................................................................................................................................... 60 Figure 4.28: Photograph of the high efficiency DA prototype board. The terminal a will be tap when R of 50 Ω output
or transformer will be used if R is 12.5 Ω. The effective DA size area is 27 mm × 24 mm. ......................................... 62 Figure 4.29: Measured versus simulated results of small-signal S-parameters across frequency range of 10 to 1800
MHz when terminated R of 50 Ω. The straight line is simulated and dotted line is referred to measured results. ....... 62 Figure 4.30: Measured versus simulated results of PAE, output power (or Pout) and gain across frequency range of
10 - 1800 MHz when terminated R of 50 Ω. The straight line is simulated and dotted line is referred to measured
results. ......................................................................................................................................................................... 63 Figure 4.31: Measured results of PAE and gain for 3 different cases when terminated R of 50 Ω. The straight line
denotes Vg = 0.44 V and Vd = 5 V, the dashed line is referring to Vg = 0.4 V and Vd = 4.6 V, and straight line with
triangle is referring to Vg = 0.44 V and Vd = 5.4 V........................................................................................................ 63 Figure 4.32: Measured versus simulated results of PAE, output power (or Pout) and gain across frequency range of
10 to 1800 MHz when terminated R of 12.5 Ω. The straight line is simulated and dotted line is referred to measured
results. ......................................................................................................................................................................... 64 Figure 4.33: Schematic diagram of DFDA with termination adjustment [23]............................................................... 65 Figure 4.34: Termination adjustment is placed at both end of the input of DA gate line to provide efficient gate line
adjustment over wide frequency range. ....................................................................................................................... 66 Figure 4.35: (a) Simplification of Figure 4.36 and (b) exclusion of eb. ......................................................................... 66 Figure 4.36: Voltage V1(ω) over normalized frequency (ω /ωc) with proper selection of Ra(ω) + jXa(ω). ...................... 66 Figure 4.37: Lumped element π-section (a) transmission line (b) lumped elements. ................................................... 67 Figure 4.38: Theoretical circuit analysis of the drain of the modified DFDA [131]. ..................................................... 69 Figure 4.39: Modified DFDA having termination adjustment network at both gate and drain lines. m-derived is
terminated at both end of the gate and drain line termination [23]............................................................................... 70 Figure 4.40: Gain response for few cases i.e. conventional DA (blue curve), applying termination adjustment at gate
line (brown curve) and termination adjustment at gate and drain line (red curve). ...................................................... 71 xi
Figure 4.41: Gain vs. frequency for various case of fo tuning. Fine selection of fo ~600 MHz (pink curve) leads to
bandwidth extension with minimum gain peaking. ....................................................................................................... 71 Figure 4.42: Gain and PAE comparison for modified DFDA and conventional DA having same input and output
artificial transmission line, DC biasing scheme at the same condition (VGS = 2.1V and VDS = 7.8V) and same
Pin = 17dBm). .............................................................................................................................................................. 72 Figure 4.43: S-parameters comparison for modified DFDA and conventional DA having same input and output
artificial transmission line, DC biasing scheme at the same condition (VGS = 2.1V and VDS = 7.8V) and same
Pin = 17dBm). .............................................................................................................................................................. 72 Figure 4.44: Photograph of the modified DFDA prototype board. The effective DA size area is 32 mm × 32 mm. The
termination adjustment network is located within yellow color circle, and DA in red color circle.................................. 73 Figure 4.45: Measured versus simulated results of small-signal S-parameters across frequency range of 100 to 900
MHz ............................................................................................................................................................................. 74 Figure 4.46: Measured versus simulated results of PAE and gain across frequency range of 100 - 900 MHz........... 74 Figure 5.1: Two-port network terminated with input and output impedances............................................................... 78 Figure 5.2: Block diagram of a system with a single feedback loop. ........................................................................... 80 Figure 5.3: Obtaining the open loop transfer function. ................................................................................................. 80 Figure 5.4: Obtaining the return level in a circuit with a single active element............................................................. 81 Figure 5.5: General diagram of an electric circuit with a current generator in parallel. The H(jωs) is determined as the
ratio of vout/iin................................................................................................................................................................ 82 Figure 5.6: General diagram of an electric circuit with a voltage generator in series. The H(jωs) is determined as the
ratio of vout/iin................................................................................................................................................................ 83 Figure 5.7: Basic DA structure in two section transistors............................................................................................. 84 Figure 5.8: (a) Basic single section DA design, and b) simplified transistor model...................................................... 85 Figure 5.9: A basic single section DA is transformed to a basic feedback oscillator i.e. Hartley Oscillator. A small
signal RF current generator i(fs) to node Vin. ............................................................................................................... 85 Figure 5.10: (a) Transfer function H(jω) magnitude and phase and b) coordinate of pole-zero of the H(jω). ............... 86 Figure 5.11: A basic two section DA, the main section is formed with Hartley Oscillator configuration and the feedback
network consists of multi-loops arrangement. ............................................................................................................. 86 Figure 5.12: Evolution of the poles in complex plane for case (a) and (b). .................................................................. 87 Figure 5.13: (a) Gate line transmission line (b) plot response of Zin imaginary part over wide frequency range (in blue
color curve). Note that real part is shown in red color curve where, it has 25 Ω at low frequency. .............................. 87 Figure 5.14: Odd mode oscillation in two section DA, and virtual ground in the middle. ............................................. 88 Figure 5.15: Analysis plot of of active nodal i.e. Vg1, Vg2 , Vd1 and Vd2. The pink color curve for both plots representing
virtual ground of gate and drain line, respectively. ...................................................................................................... 88 Figure 5.16: Equivalent circuit model of two section DPA for odd mode oscillation. The middle reference plane is
ground plane. .............................................................................................................................................................. 89 Figure 5.17: (a) Gate line transmission line (b) plot response of Zin imaginary part over wide frequency range (in blue
color curve). Note that real part is shown in red color curve where, it has 25 Ω at low frequency. .............................. 89 Figure 5.18: Three section DPA arrangement to explain odd mode oscillation. .......................................................... 90 Figure 5.19: Analysis plot of of active nodal i.e. Vg1, Vg2 and Vg3. (a) shows odd mode oscillation condition for (+,0,-)
mode and (b) shows (+,-,+) mode. .............................................................................................................................. 90 Figure 5.20: (a) pole-zero map (O zeros, X poles) corresponding to the small-signal stability analysis of the original
circuit. (b) pole-zero map (O zeros, X poles) corresponding to the small-signal stability analysis of the stabilized
circuit. .......................................................................................................................................................................... 92 Figure 5.21: Evolution of the real part of critical poles versus Pin for the original circuit and the three stabilization
configurations, evolution of the small-signal gain @ 760MHz versus Pin and frequency of input drive is 200MHz. ..... 92 xii
Figure 5.22: a) Pole/zero map showing the frequency division for fin = 500 MHz, Pin = 17.1 dBm and ΓL = 0.75 ∠ 180º.
b) Unstable (circles) and stable (crosses) values of ΓL for fin = 500 MHz and Pin = 17.1 dBm. .................................... 93 Figure 5.23: Frequency division experimentally found in DA for fin = 521 MHz, Pin = 16 dBm and ΓL = 0.75 ∠ 180º. ... 93 Figure 5.24: Simplified design schematic of the high-efficiency LDMOS DA. The second version of the circuit includes
the stabilization resistor Rstab at second section of the DA. ......................................................................................... 94 Figure 5.25: The photograph of the high efficiency LDMOS DA. The size of the board is 27 mm × 13 mm. ............... 95 Figure 5.26: PAE simulation results of original circuit and the three stabilization configurations for Pin = 19 dBm. PAE
measurement results of stabilized amplifier for Pin = 19 dBm. ..................................................................................... 95 Figure 5.27: Example of measured of power spectra at 700 MHz, and there is no oscillation is reported. ................. 96 Figure 6.1: Several gain stage configuration used in DA (a) common source (b) cascode [171] (c) cascaded two
identical transistors common source gain [174] (d) cascaded non-identical transistors and inter-stage tapered
impedance [14]. ........................................................................................................................................................... 98 Figure 6.2: Schematic of cascaded distributed power amplifier with non-identical transistors and controlled inter-stage
tapered impedance for wideband solution. ................................................................................................................ 100 Figure 6.3: Configuration of 2-stage non-identical transistor where the first is high-fτ and second transistor is power
transistor, inclusion of an inter-stage matching configuration with tapered termination. ............................................ 100 Figure 6.4: Schematic to illustrate the impedance Zin which seen by the current source ii. ....................................... 100 Figure 6.5: Simplified of Figure 6.4 to give explanation of Zint, and ZT is consists of three elements i.e. jX, jB and G.
.................................................................................................................................................................................. 101 Figure 6.6: The real (a) and imaginary (b) part of Zint evaluated at cut-off frequency versus B (susceptance) for few
cases of X (for fixed G of 0.018). ............................................................................................................................... 101 Figure 6.7:Zint real and imaginary parts with tapered impedance (red line) and fixed termination (blue line). ............ 102 Figure 6.8: Schematic to illustrate the impedance Zint is seen by the current source ii. ............................................ 103 Figure 6.9: The real (a) and imaginary (b) part of Zint for circuit shown in Figure 4.8 for m = 2.4, evaluated at ωc versus
B (susceptance) for few cases of X (for fixed G of 0.012). ........................................................................................ 103 Figure 6.10: Small signal model for gain analysis including two non-identical transistors with inter-stage tapered
impedance. ................................................................................................................................................................ 104 Figure 6.11: Roots of G(s) for (a) fixed termination (ZT = 50 Ω) and (b) tapered termination for few cases of m. ..... 106 Figure 6.12: A perturbation current in is injected at active nodal of gate power transistor. Current probe impedance
seen Zp can be obtained by dividing vn/in................................................................................................................... 107 Figure 6.13: (a) Magnitude and phase of closed-loop frequency response Zp with 50 Ω load termination (b)
Associated pole-zero map (for simplicity only the positive imaginary part of the complex plane is plotted). Black
triangles: poles for 50 Ω load termination; circles: zeroes for 50 Ω load termination; diamonds: evolution of critical
pole versus the phase of a fully reflective load. ......................................................................................................... 107 Figure 6.14: Simplified schematic of the DPA; high-fτ transistors cascaded to the power transistor with inter-stage
tapered impedance. The gate and drain line are formed with constant-k ladder network for 50 Ω input and output
impedances. .............................................................................................................................................................. 109 Figure 6.15: Simulation results of drain voltage of each non-identical transistors for inter-stage tapered (straight line
with circle) and fixed termination impedance (straight line only). ............................................................................... 110 Figure 6.16: Simulation results of power performance i.e power, gain and PAE of cascaded DPA with inter-stage
tapered (straight line with circle) and fixed termination impedance (straight line only). ............................................. 110 Figure 6.17: 4-layer high density Rogers PCB; metal Layer 1 and 4 thickness is 0.06 mm, and Layer 2 and 3 having
thickness of 0.035 mm, and thus, total PCB thickness is ~1.4 mm. .......................................................................... 111 Figure 6.18: Photograph of the prototype of DPA having high-fτ transistors cascaded to the power transistor with
inter-stage impedance termination. The DPA size area is 38 mm × 22 mm. ............................................................. 112 Figure 6.19: Measured vs. simulated of S-parameters of the DPA having high-fτ transistors cascaded to the power
transistor with inter-stage tapered termination........................................................................................................... 113 xiii
Figure 6.20: Measured vs. simulated of power performance of the DPA having high-fτ transistors cascaded to the
power transistor with inter-stage tapered termination. ............................................................................................... 113 Figure 6.21: Measured results of power performance i.e. power and PAE with sweeping the Pin drive (at 1 GHz) of the
DPA having high-fτ transistors cascaded to the power transistor with inter-stage tapered termination. .................... 114 Figure 6.22: Example of measured of power spectra at 400 MHz and there is no oscillation is reported. The output
signal is attenuated with external 30 dB attenuation pad to avoid damage to the spectrum analyzer. ...................... 114 Figure 6.23: Summarized state-of-art work of output power-frequency DPA. ........................................................... 115 Figure 6.24: Optimum power condition of the device current source loaded by Ropt. ................................................ 116 Figure 6.25 : The virtual impedance seen by the current source i1(t) in both directions Zu(1) and Zr(1), respectively
when two current sources are combined to a single node. ........................................................................................ 117 Figure 6.26: Synthesize drain transmission line to load each device generator by its optimum Ropt(k)(ω). ................. 118 Figure 6.27: General diagram of high power DPA circuit proposal. The term n and N are referring to number of stages
in cascaded and section, respectively. Impedance transformer may included when the termination is less than 50 Ω.
.................................................................................................................................................................................. 119 Figure 6.28: Synthesize drain transmission line to load each device generator by its optimum Ropt(k)(ω) for n = 3. ZL is
identified for optimum power performance in CAD simulator..................................................................................... 120 Figure 6.29: Simplified schematic the new DPA topology. The input drive of the VCO is ~8 dBm, and non-uniform
gate line is adopted from [19]. Two non-identical high-fτ transistors (ATF54143 and ATF511P8) are cascaded to the
power transistor (GaN device). Output impedance is terminated to ZL, which will be coupled to transformer/filter. .. 121 Figure 6.30: Simulation analysis of S-parameters for the new topology DPA across 0.1-2 GHz, and ZL of ~14 Ω is
required for optimum performance. ........................................................................................................................... 122 Figure 6.31: Simulation analysis of power performance i.e. power, gain, PAE for the new topology DPA across
0.01-2 GHz, and ZL of ~14 Ω is required for optimum performance. ......................................................................... 122 Figure 6.32: Layout artwork of the DPA topology for all layers. Additional DC routing is done via layer 3, where layer 2
is RF grounding. ........................................................................................................................................................ 123 Figure 6.33: Photograph of the prototype of new topology DPA. The DPA size area is 38 mm × 32 mm. ................ 124 Figure 6.34: Example of measurement results of load pull impedance determination for 100 MHz and 1 GHz,
respectively. The maximum power occurred at ℜ{ZL} of 25 Ω. .................................................................................. 125 Figure 6.35: Measurement results of highest output power with load pull impedance determination across the entire
bandwidth. The maximum power occurred at ℜ{ZL} of ~25 Ω in measured level. ..................................................... 126 Figure 6.36: Measurement results of optimum power performance i.e. power, gain and PAE with load pull impedance
determination across the entire bandwidth. The maximum power occurred at ℜ{ZL} of ~12 Ω in measured level…..126 Figure 6.37: Measured vs. simulated of S-parameters of the DPA topology terminated to 50 Ω load.......................127 Figure 6.38: Measured vs. simulated of power performance of the DPA topology terminated to 50 Ω load………...127 Figure 6.39: Measured results of power performance i.e. power and PAE with sweeping the Pin drive (at 1 GHz) of
the new DPA topology………………………………………………………………………………………………………….128
Figure 6.40: Basic topology of bipolar Class E power amplifier with shunt capacitance circuit...................................129 Figure 6.41: An ideal Transformer with a filter which constitutes a “transformer/filter”. ............................................. 129 Figure 6.42: An ideal transformer/filter with Transducer power gain (TPG) characteristics. ...................................... 129 Figure 6.43: Darlington’s description of lossless two-port transformer/filter, where p = σ + jω (complex variable) [184].
.................................................................................................................................................................................. 130 Figure 6.44: Circuit Topology which is dictated by the real part of the Positive Real Impedance ZB. ........................ 132 Figure 6.45: Piecewise linearization of RM(ω). ........................................................................................................... 133 Figure 6.46: Circuit Topology of transformer/filter with optimized element values ..................................................... 136 Figure 6.47: Optimized transducer power gain of the lossless [transformer/filter] with ideal circuit components....... 137 xiv
Figure 6.48: Actual implementation of transformer/filter. ........................................................................................... 137 Figure 6.49: Simulated (thin line) vs, measured (thicker line) performance of transformer/filter, (a) insertion loss
(b) group delay within operating bandwidth. .............................................................................................................. 138 Figure 6.50: Simulation performance harmonic filtering up beyond passband. The thick line is referring with usage of
discrete high Q inductors and thin line is for lumped transmission line ..................................................................... 139 Figure 7.1: Simplified topology of cascode, where a common-source FET is coupled to the active load with
common-gate configuration. ...................................................................................................................................... 143 Figure 7.2: Simplified cascode topology analysis at low frequency. .......................................................................... 144 Figure 7.3: Current combining to a common node R, with cascode configuration, for n section. .............................. 145 Figure 7.4: Circuit showing multi-current sources to combine at a single load termination, R = 50 Ω....................... 146 Figure 7.5: DC biasing condition for cascode topology. ............................................................................................ 146 Figure 7.6: Simulated results of power performance between cascode and common-source topology. ................... 147 Figure 7.7: Simplified design schematic of cascode with combination of current combining approach to a single load
termination................................................................................................................................................................. 147 Figure A.1: Typical 8-layer structure of PCB. ............................................................................................................ 148 Figure A.2: Example of poor grounding. .................................................................................................................... 149 Figure A.3: Star point grounding. ............................................................................................................................... 149 Figure A.4: Parallel connection grounding. ................................................................................................................ 149 Figure A.5: Multiple ground vias. ............................................................................................................................... 150 Figure A.6: Via-holes used in two-way radio applications.......................................................................................... 150 Figure A.7: (a) parallel runners (b) perpendicular runners. ........................................................................................ 151 Figure A.8: Magnetic coupling of the runners (a) larger loop area (b) minimized loop area ...................................... 152 Figure A.9:Inductor placement to avoid magnetic coupling. ...................................................................................... 152 Figure A.10: (a) Poor placement (b) Good placement. .............................................................................................. 153 Figure A.11: Ground underneath component pad has been removed. ...................................................................... 153 xv
List of Tables
Table 2.1: Typical power obtainable from device technologies to achieve target of RL,opt = ~50 Ω................................ 3 Table 2.2: Summarized measurement results of broadband paralllel-circuit class E PA with reactance compensation.7 Table 2.3: Summarized measurement results of broadband shunt C-LC class E UHF [18]. ......................................... 9 Table 2.4: Summarized measurement results of power performance and ACPR of the broadband high linearity and
efficiency PA employing Cartesian feedback [19]. ....................................................................................................... 11 Table 2.5: Summarized measurement results of multi-stage broadband PA [22]. ....................................................... 12 Table 2.6: Summarized measurement results of the BA [62]. ..................................................................................... 14 Table 3.1: Extraction of Zin(ω) and Zout(ω) of high fτ transistor and power transistors. Note that Rin and Cin in paralell
form. .............................................................................................................................................................................. 9 Table 4.1: Zu(k)/R and Zu(k)/R for various Ik and θk selection (k = 1, 2, 3 and 4). ........................................................... 48 Table 4.2: Summary drain line network elements for various load termination, R. n section is 4. Cd(k) is the external
shunt capacitance placed parallel to the transistor…………………………………………………………………………...54
Figure 4.3: Summary performance of power and PAE over the 100-800 MHz for the state-of-art of DA realizations..75 Table 6.1: Comparison of high power-gain response DPA works…………………………………………………………..98
Table 6.2: Design goal requirement of the first DPA development..............................................................................108
Table 6.3: Design goal requirement of the second DPA development........................................................................119
Table 6.4: Summary performance of the new DPA topology......................................................................................128
Table A.1: Typical signal lines for layer structures. ................................................................................................... 148 Table A.2: Dimension of via-holes. ............................................................................................................................ 150 Table A.3: Width of the runners used in the 10 W PA design. ................................................................................... 151 xvi
Chapter 1.
Introduction
Traditionally, two-way public safety radios are operated in a single band. In the USA, as an example, the
rural Police operates at VHF (Very High Frequency) band i.e. 150 MHz whereas the urban Police uses
the UHF (Ultra High Frequency) band i.e. 800 MHz, respectively. Hence in an occurrence of an
emergency situation, both agencies will not be able to communicate with one another. This is due to the
distinctive frequency band they operate in. As such, interoperability among the public safety agencies is a
big issue in the USA. Thus, there is a strong market drive for a single radio that can operate in any
frequency band i.e. SDR (Software Defined Radio) 1 . Apart from the public safety agencies, there is a big
push by military, army, navy and air force necessitate absolute demand for a SDR radio for effective
communication.
Multiband radios (145-450 MHz) are commonly available from Ham radio vendors. However, the RF and
reliability performance are not adequate for public safety market. Similarly, Joint Tactical Radio System
(JTRS) [1] is also not suitable for public safety due to the poor RF performance. Hence, this inadequate
creates demand for a good RF reliability performance SDR radios for public safety agencies. SDR was
coined by Joseph Mitola, who published the first paper on the topic in 1992 [2]. Though the concept was
first proposed in 1991, SDR have their origins in the defense sector since the late 1970s in both U.S. and
Europe. One of the first public software radio initiatives was a U.S. military project named Speak-Easy 2 .
Conventional SDR architecture consists of multiple filters, Low Noise Amplifier (LNA), mixers, Power
Amplifiers (PAs) and Voltage Controlled Oscillator (VCO). This architecture is amenable into two bands
i.e. VHF and 800 MHz. Many radio models are needed to cater for the entire public safety band such as
VHF (136-176 MHz), UHF1 (380-520 MHz) and UHF2 (700-800 MHz). However, this architecture is too
costly and bulky to cover all the bands in a single radio. The most challenging part of SDR architecture is
the design of a single broadband PA architecture. Next generation SDR PA applications requires
broadband, efficient and high output power, and other RF parameters in small size area implementation.
Motorola Research Center focuses on Distributed Amplifier (DA) to meet the requirements of SDR PA [3].
DAs have been used extensively for many years in variety broadband system applications, however,
these amplifiers have never demonstrated high power and efficiency performance [4] - [10]. DA theory
does not inherently limit output power and efficiency performance obtainable, but proper circuit design
and device selection must be considered [11] – [13].
1.1 Objective of This Work
This work is fully supported by Motorola Research Center, Malaysia in collaboration with ITHE, RWTH
Aachen University, Germany. The primary objective of the work is to develop high power (i.e. 10 W and
30 W), efficient and gain block PA, for SDR PA applications 3 . The amplifier must be stable, and allows
VCO to be coupled directly to the PA input, and the level from the VCO is ~8 dBm.
To achieve high output power covering bandwidth of 40-2000 MHz requires both improved circuit design
techniques and proper device selection. Novel circuit topologies to meet these requirements are
proposed in this thesis [14] - [15]. Broadband amplifiers demand wide-bandwidth (high transition
frequency fτ) and high-power (high breakdown voltage Vbk). The combination of high power and wide
1
SDR have significant utility for the military and cell phone services, both of which must serve a wide variety of changing radio
protocols in real time [1].
2
The primary goal of the Speak-Easy project was to use programmable processing to emulate more than 10 existing military radios,
operating in frequency bands between 20 and 2000 MHz.
3
SDR operating frequency of Motorola applications is 100-1000 MHz, but this thesis focuses for operating frequency from
40 - 2000 MHz, which targeted for next generation SDR PA solutions.
1
bandwidth is best addressed with wideband-gap semiconductor materials such as Gallium Nitride (GaN)
[12], [16].
This thesis explores basic bandwidth limitation analysis and introduces various broadband PAs design
[17] - [20], before begin of the DA works. This gives an understanding on the bandwidth limitation and the
conceptual target to achieve broadband amplifiers while other RF parameters (i.e. output power, gain,
efficiency, stability, etc) are fulfilled. Besides that, few novel DA topologies are invented in this thesis, and
the theoretical analysis is developed with simplified Field Effect Transistor (FET) model. A practical
design methodology is presented, it is essential for DAs development without any tuning/optimization in
hardware level [21].
A technique concept to combine multi-current sources to a single load termination is discussed, and
generalized design equation of virtual impedances is developed to design high efficiency DA [13]. Due to
the need of the DA, an impedance transformer applying coupled transmission line with loading of stepped
impedance transmission line is proposed, exhibiting six minima zero reflection coefficient [22]. Another
concept topology to achieve high efficiency with low DC supply voltage is introduced, which so called
Dual Fed DA (DFDA) with termination adjustment [23].
Origin nature of oscillation in DA is analyzes with pole-zero identification method and explanation of odd
mode oscillation is give in [24]. Practical realization of high efficiency DA is investigated where parametric
oscillation is exhibited in measurement level due to gain expansion [25]. Suitable stabilization circuit is
investigated to minimize electrical performance degradation while ensure good margin of stability [25].
Two generation of DA were designed for SDR applications with GaN technology. Since this DA is meant
for high output power, it is suitable to be called as distributed power amplifier (DPA). The first generation
DPA circuit yield ~10 W power, gain of 32 dB and PAE 4 of 15-30 % [14]. The second generation DPA
circuit achieved ~20 W power, PAE of 30-55 %, gain of 37 dB [13], [15]. The second generation DPA
circuit employing transformer/filter 5 exhibited 1.1 ± 1 dB across the bandwidth [26] – [27].
1.2 Thesis Organization
Chapter 2 discusses the bandwidth limitation analysis i.e. load line, device technology, etc. Various
broadband design techniques including broadband switched mode PA, linear and efficient PA, multi-stage
PA, and Balanced Amplifier (BA) are introduced [17] - [20].
Chapter 3 reviews basic DA concept, and theoretical analysis from image impedance method [28],
classical model to explain DA principal i.e. Beyer model [4], Niclas model [6] and McKay model [29]. End
of the section, practical design methodology of the DA is discussed.
Chapter 4 discusses analysis of virtual impedance due to multi-current source, and a technique to
increase DA efficiency. Design example of high efficiency DA is given as well. DFDA with termination
adjustment topology is introduced.
Origin of stability analysis of DA applying pole-zero identification method and parametric oscillation
analysis of high efficiency DA are discussed in Chapter 5.
Chapter 6 proposes two novel topologies for SDR applications, to meet ~10 W and ~20 W output power,
respectively [13] - [15]. These amplifiers demonstrated best in state-of-art of DA power performance.
Chapter 7 concludes the thesis and discusses future work beyond this Ph.D work e.g. high power
cascode DPA.
Appendix A is mainly a review on layout guidelines for practical RF/Microwave circuit design.
4
5
PAE (power-aided-efficiency) is defined by RF output power over total input power (DC and RF input).
The transformer is built with semi-analytical of Real-Frequency technique (RFT) [26], which requires small size area realization.
2
Chapter 2.
Broadband Amplifier Limitations and Designs
Bandwidth limitation in designing a broadband amplifier can be addressed through circuit design and
device characteristics. Broadband amplifier requires careful considerations, and basically, the design over
a broad frequency range is a matter of properly designing the matching networks, in order to compensate
for the variations of forward transmission S21 with frequency. Two techniques that are commonly used to
design broadband amplifiers are matching network compensation, and negative feedback [32]. Matching
network compensation involves mismatching the input and output networks to compensate the changes
with ⏐S21⏐, and the network must give the best input and output VSWR.
The realization of high power devices requires an appropriate selection of semiconductor materials to
properly balance the heat transfer across the device itself [30]. Large-scale RF and microwave power
device production is actually based on Silicon (Si), Gallium Arsenide (GaAs), Latheral Diffusion MOSFET
(LDMOS), while great research interest is devoted of high power density devices using wide-bandgap
materials such as Silicon Carbide (SiC) and Gallium Nitride 6 (GaN) [30]. A higher bandgap corresponds
to a higher breakdown field, which in turns implies the capability of the device to allow higher output
voltage swings and thus attain higher output power levels. Moreover, high breakdown voltage results in
larger output impedance values for a given current density, making the device matching easier for
broadband applications [31]. Therefore, the selection of high fτ -Vbk device technology is a good solution
[31].
In this chapter, basic limitations on bandwidth are explained. A few works subject to broadband PAs
including switched mode PA, linear and efficient PA, multi-stage PA, and Balanced Amplifier (BA) are
discussed. These amplifiers demonstrated excellent power performance over wide frequency bandwidth,
and best performance in state-of-art of PA within VHF/UHF operating bandwidth [17] – [20].
2.1 Bandwidth Limitation Analysis
To achieve broadband performance from a single ended device, the load impedance RL,opt must be close
7
to ~50 Ω over wide frequency range. RL,opt = (Vbk - Vk)2/2Pout , therefore, scaling the device periphery is
possible to achieve RL,opt ~50 Ω by means of DC voltage. But this may imply lower output power. One can
increase output power with the increase of DC voltage while keeping RL,opt ~50 Ω. Table 2.1 summarizes
the typical broadband performance from various device technologies and the device periphery.
Device technology
Vbk (V)
Vk (V)
IDSS (mA/mm)
Device periphery (mm)
Pout (W)
GaAs MESFET [32]
18
1
300
0.75
0.3
InP pHEMT [33]
12
1
500
0.45
0.3
GaN HEMT [34]
50
5
500
1.8
5
Table 2.1: Typical power obtainable from various device technologies to achieve target of
RL,opt = ~50 Ω.
6
7
GaN has established itself as a strong contender for such applications, because of its large electron velocity (>1×10 cm/s),
bandgap (3.4 eV), breakdown voltage Vbk >50 V for current-gain cut-off frequency fτ=50 GHz, and sheet carrier concentration
13
-2
(ns >1×10 cm ) [16].
7
Vbk and Vk are referring to break-down voltage and knee voltage, respectively.
3
Since fτ varies inversely with Vbk, a high power broadband amplifier must use low fτ power transistors,
and larger device periphery are needed to achieve to RL,opt ~50 Ω. Consequently, the transistor has a
large input capacitance Cgs, given by
C gs =
gm
2πf τ
(2.1)
where gm is the device trans-conductance.
As the Cgs is directly proportional to gm, one possible way of increasing bandwidth is to decrease device
extrinsic trans-conductance by using either capacitance [35] or resistive degeneration. These two
techniques offer broadband PAs solution with trade-off gain for bandwidth.
Bandwidth analysis is carried out to provide optimum matching condition for wide frequency range. The
inherent bandwidth (BW)i is the bandwidth obtained under conjugate matching conditions where the
matching loads terminate the two port device [36]. A conjugate match means ΓS = Γ*IN or admittances
YS =Y*IN = G - jB. G and B represent the conductance and susceptance under conjugate match condition,
respectively. Figure 2.1 shows equivalent network under conjugate matched conditions. ΓS and ΓIN are the
reflection coefficients of the matching network and the device, respectively. YS and YIN are the
corresponding admittances. The inherent bandwidth is given by
( BW )i =
fo
Q
(2.2)
where ωo (ωo=2πfo) is the angular frequency in which conjugate match values were obtained and Q is the
quality factor of the parallel network [36] defined by
Q = ωo RC =
R
ωo L
(2.3)
By substituting (2.3) into (2.2) one can express the inherent bandwidth as
( BW ) i =
2 f oG
(2.4)
|B |
where R= 1/2G and |B| = ωoC = 1/ωoL.
It is shown in (2.2), that in order to achieve a wide bandwidth, Q of the network has to be low enough.
Similarly from (2.4), it should be noted that conductance G must be high enough susceptance B must be
kept at low level in order to maximize the bandwidth.
VIN
YIN
YS
ΓS
ΓIN
Figure 2.1: Equivalent network of the input port under conjugate matched conditions.
4
2.2 Broadband switched-mode amplifier
The concept of Class E switched mode was introduced by Sokal in 1975 [37]. It was followed by a
detailed design analysis for an idealized topology given by Raab [38]. Class E with shunt capacitance is a
good choice to achieve high efficiency solution of RF power amplifier [39] – [43]. The Class E switching
PA concept aims to achieve high efficiency by designing the proper device (collector or drain) voltage and
current waveforms so as to minimize losses on the active device since it is a main contributor to the
efficiency degradation [38]. The conventional design of a high efficiency switched-mode tuned PA
requires a high QL-factor to satisfy the necessary harmonic impedance conditions at the output device
terminal. However, if a sufficiently small value of the QL-factor can be chosen, a high efficiency broadband
operation of the Class E PA can be realized without trade-off the switching action.
Several works have demonstrated high efficiency switched-mode amplifier [41], [44]. In the following
sections, two design techniques of switched mode will be discussed which demonstrated experimentally
best in state-of-art of broadband VHF and UHF frequency region, respectively within small size area and
low cost implementation [17] – [18].
2.2.1
Parallel-circuit class E with reactance compensation technique
The parallel-circuit Class E represents a subclass of a general Class E with a finite DC-feed inductance
when there is no additional reactive phase-shifting element connected in series to the L0C0-filter [45],
shown in Figure 2.2. In the parallel-circuit Class E PA, the transistor Q1 also operates as an on-to-off
switch and the shapes of the current and voltage waveforms provide a condition when the high switch
current and high voltage does not overlap [46]. The load network consists of a parallel inductance L, a
shunt capacitance C, a series L0C0-resonant circuit tuned to the fundamental and a load R.
VDC
L
L0
Q1
C0
R
C
Figure 2.2: Basic diagram of load network of parallel-circuit Class E power amplifiers.
To describe reactance compensation circuit technique [47], consider the simplified equivalent load
network with a series resonant L0C0-circuit tuned on the fundamental and a shunt LC-circuit providing a
constant load phase angle. The reactance of the series and shunt resonant circuits varies with frequency,
increasing in the case of series circuit and reducing in the case of loaded parallel circuit near the resonant
frequency ω0, as shown in Figure 2.3, by curve 1 and curve 2, respectively. Near the resonant frequency
ω0 of the series circuit with positive slope of its reactance, the slope of shunt circuit reactance is negative.
With a proper choice of the circuit elements, a constant load angle over a very large frequency bandwidth
is established. It needs only to calculate the optimum loaded quality factor of the series L0C0-filter to
maximize the frequency bandwidth.
5
The load network input admittance Yin = 1/Zin can be written as
⎛
1
1
+
Yin = ⎜⎜ jω C +
jω L
R + jω ′L0
⎝
⎞
⎟⎟
⎠
(2.5)
where
⎛
ω2 ⎞
ω ′ = ω ⎜⎜1 − 02 ⎟⎟
ω ⎠
⎝
where ω 0 = 1 /
(2.6)
L0 C 0 is the resonant frequency.
Xin
2
1
ω
ω0
Figure 2.3: Reactance compensation principle using series and parallel resonant circuits.
The parameters of the series L0C0-resonant circuit must be chosen to provide a constant phase angle of
the load network over a broadband frequency bandwidth. This bandwidth will be maximized if it is at the
resonant frequency ω0
dB (ω )
dω
(2.7)
=0
ω =ω 0
(
)
where B (ω ) = ImYin = − 1 − ω 2 LC / ωL is the load network susceptance.
As the final result, the series capacitance C0 and inductance L0 [20], can be deduced to
L0 = 1.026
R , and
(2.8)
ω
C0 = 1/ω 2 L0 .
(2.9)
In this experiment, a test board using FR-4 material was fabricated, where dielectric constant εr of 4.5 and
thickness h of 14 mils. Basically the board consists of the RF input and output ports, two voltage supply
feeds, two-section low-pass input matching and output load network with three-stage output matching.
Figure 2.4 shows photograph of broadband parallel-circuit class E power amplifier with reactance
compensation, and the summary measured results are given in Table 2.2.
6
GND
VDC
55 mm
45 mm
RFout
RFin
Class E load
network
Input matching
Figure 2.4: Photograph of prototype board of broadband parallel-circuit class E PA with reactance
compensation.
Parameters
Performance
Operating Bandwidth (MHz)
134 - 174
Output Power (W)
8
Efficiency (%)
>74
Power Flatness (dB)
± 0.8
Stability with 10:1 VSWR
Stable
Robustness with 10:1 VSWR
No degradation
Table 2.2: Summarized measurement results of broadband parallel-circuit class E PA with
reactance compensation [17].
2.2.2
Excessive capacitance absorption with shunt C-LC network
Practically, for low microwave frequency applications, available packaged transistor for high power
8
operation, does not meet class E switching action [48]. COSS of the device is higher than the class E
switching capacitor when configuring the class E load network in UHF operating range i.e. additional
9
shunt capacitor of 50 pF needs to be compensated or absorbed to the output load network .
A novel topology of the output load network to absorb excessive device capacitance while having
broadband switching action of class E is introduced in [18], as shown in Figure 2.5. The nominal switching
conditions for class E gives us the condition for an optimum load to show the transistor (switch) and the
capacitance in parallel. That load network must include a 50° load angle that will be converted to 33°
when the effect of shunt capacitor is included. The Lchk can be included in the matching network if
desired. In Figure 2.5, RL will be the load where we will develop the output power, LB and CB will be the
main output resonant circuit and LA will compensate the slope to show a constant angle (49º) for the input
impedance in broadband. The CA capacitance can be used simply to avoid a DC short from VDC-Lchk-LA
path or better it still, can be used as a free variable to get that function, and as well as to reach other
goals as enhanced efficiency [18]. Finally, Cd is included as an “excess of capacitance” from the device.
8
Coss = Cds + Cgd, that typically tested at frequency of 1 MHz and Vgs = 0V (for LDMOS device typically). Cds is drain to source, and
Cgd is gate to drain capacitances.
9
The element values are calculated to deliver power of 4 W with 7.2 V supply voltage with reference to [48].
7
VDC
Lchk
LB
Cdx
CB
LA
Q1
R
CA
Figure 2.5: Broadband class E amplifier with shunt C-LC network providing constant load angle
and absorbing excessive capacitance in the device.
The broadband load networks parameters [18] are given by
L Bx =
8 ⋅ 10 − 4
2
ω x C x 2 ( N ratio − 1)
C Bx = 1250 C x
2
⎡175 (tan( ψ x ) 2 + 1) 0 .5 + 175 (tan( ψ x ) 2 + 1) 0 .5 C x N ratio tan( ψ x ) + ⎤
⎢
⎥,
2
⎢⎣.. + 98 C dx N ratio + 98 C dx N ratio tan( ψ x )
⎥⎦
N ratio − 1
175 (tan(ψ x ) 2 + 1) 0.5 C x tan(ψ x ) + ..
+ 175 (tan(ψ x ) 2 + 1) 0.5 C x N ratio tan(ψ x ) ,
(2.10)
(2.11)
+ .. 98 C dx N ratio + 98 C dx N ratio tan(ψ x ) 2
L Ax = 7 N ratio
ωx
Rx =
2
(tan( ψ x ) + 1 ) 2
C x − 25 tan (ψ x )C x + ..
⎡ 25 tan (ψ x )N ratio
⎤
⎢
2
0 .5
2
0 .5 ⎥
⎣ + 7 C dx N ratio (tan( ψ x ) + 1 ) − 7 C dx (tan ψ x ) + 1 ) ⎦
28(tan(ψ x ) 2 + 1) 0.5 , and
C xω x
C Ax = ( 2 ⋅ 10 − 2 N ratio − 2 ⋅ 10 − 2 )
,
(2.12)
(2.13)
+ 175 (tan ψ x ) 2 + 1) 0.5 C x tan(ψ x )
tan(ψ x ) 2 + 1
(2.14)
where Cdx is total of switching capacitor (Cx) and extra capacitance. ωx is frequency and ψx is load angle.
Nratio is ratio of LA impedance versus CA impedance (usually high if CA is desired for decoupling only)
In that way, magnitude load of 6.6 Ω to deliver output power of ~4.8 W, and load angle near 50° are
achieved across desired frequency range, as shown in Figure 2.6.
8
Figure 2.6: The load output network is designed to show ideal impedance to the switch for the
complete broadband (400-470MHz) in this example.
33 mm
A test board using FR-4 material was fabricated, where dielectric εr of 4.5 and thickness h of 14 mils.
Basically the board consists of the RF input and output ports, supply and bias voltage feeds, input
matching and output load network with three-stage output matching. Figure 2.7 shows photograph of a
broadband shunt C-LC class E UHF PA, and summary measured results are given in Table 2.3. An
analysis of output voltage and measurement techniques are explained in [49] - [50], respectively.
98 mm
Figure 2.7: Photograph of prototype of broadband shunt C-LC class E UHF PA.
Parameters
Performance
Operating Bandwidth (MHz)
390 – 470
Output Power (W)
4
Efficiency (%)
>75
Power Flatness (dB)
± 0.7
Stability with 10:1 VSWR
Stable
Robustness with 10:1 VSWR
No degradation
Table 2.3: Summarized measurement results of broadband shunt C-LC class E UHF [18].
9
2.3 Broadband High Linearity and Efficient amplifier
To design a high linearity and high efficiency RF PA with wide bandwidth is a real challenge. This section
10
explains the design technique to achieve 1 W broadband (800-900 MHz) PA to meet TETRATM, [51],
[75]. A three-stages GaAs HBT (Gallium Arsenide Heterojunction Bipolar Transistor) RF PA with
Cartesian feedback in close-loop form is the main architecture of the design. An adaptive bias technique
was used in the RF PA design in order to achieve high linearity while preserving good efficiency. There
are few works that have been reported to achieve good linearity and high efficiency PA [52] – [55].
However, this work demonstrated highest power and efficiency while preserving good ACPR to meet
TETRATM standard over wide frequency range operation [51].
Adaptive bias technique allows the change of quiescent current of a device with respect to input power
levels. In other words, the low quiescent current with low output power level and the increasing quiescent
current with high output power can be achieved. Therefore, the power amplifier consistently maintains
adequate quiescent current for the amplifier to operate in near saturation region. This technique
simultaneously provides both high linearity and efficiency characteristics over a broad range of power
levels [57]. The principle operation of adaptive bias technique is described in Figure 2.8.
For multistage amplifiers, similar techniques can be employed for each stage of the amplifier. In this work,
three-stage power amplifier is chosen to achieve high gain, high output power and high efficiency at the
same time. A smart dc bias regulator is built to provide necessary bias voltage to each power amplifier
with respect to input power levels. Each stage of the amplifier operates in deep class AB at pretty low
quiescent current. As soon as input RF power is applied to the amplifier, the bias point is shifted to
produce optimum power performance.
A broadband matching network with loaded Q of 5 was chosen to transform optimum load impedance ZOL
to 50 Ω load termination. The load impedance is obtained from load pull simulation result, and well
correlated with measurement data. From the calculation (and for more margin), loaded Q of 5 is selected
to achieve wideband matching characteristics from 800 to 900 MHz frequency range [58]. A three-stage
low pass matching network is used to transform the ZOL to 50 Ω. The first matching component is a
tapered microstrip line that significantly increases the efficiency for a wide frequency band. A second
harmonic trap is introduced at the final stage feeding line. The bonding wires together with the external
capacitor form a series resonator that be tuned at second harmonic frequency in order to increase
efficiency and reduce spurious output.
Figure 2.8: Block diagram of adaptive bias technique.
RF power amplifier with Cartesian feedback in close-loop form is the main architecture of the design.
Simulation modeling of the ACPR performance of the closed loop PA employing Cartesian feedback
model across wide frequency spacing is introduced [19]. The prototype board of the RF amplifier with
Cartesian feedback (JavelinTM IC) is fabricated using FR-4 material which has a dielectric constant εr of
10
TM
TETRA (Trans-European Trunked RAdio) [56] standard requires a very high degree of linearity compared with the cellular and
TM
satellite based systems. The TETRA uses a TDMA (Time Division Multiple Access) and digital modulation scheme known as π/4
DQPSK which is a special form of Phase Shift Keying (PSK)with Adjacent Channel Power Ratio (ACPR) of more than -65 dBc.
10
4.5 and a thickness h of 14 mils, as shown in Figure 2.9. Summary measurement result of the closed loop
performance is given in Table 2.4.
55 mm
PA
40 mm
Cartesian
feedback
Isolator
Harmonic
Filter &
Switch
RFout
Figure 2.9: Test board of the broadband high linearity and efficiency PA employing Cartesian
feedback.
Frequency (MHz)
Parameters
800
850
900
1 dB compression
point [dBm]
34.7
34.6
34.5
PAE [%]
37.4
37.3
35.1
ACPR [dBc]
76.9
77.5
78.9
Maximum power [dBm]
36.5
36.4
36
Table 2.4: Summarized measurement results of power performance and ACPR of the broadband
high linearity and efficiency PA employing Cartesian feedback [19].
2.4 Multi-stage broadband amplifier
11
This section explains to achieve broadband high efficiency and high harmonic suppression
with
multi-stage PAs 12 [20]. Due to low input signal from VCO, first stage transistor with 10 dB gain stage is
used. Second and final stage transistors have a gain that decreases with increasing frequency. The
specifications for a good input and output match will require that the inter-stage matching network
between the second and final stage PA must provide a gain having positive slope with increasing
frequency to compensate for the transistor roll-off [36]. A novel idea for phase compensation is introduced
in between of the broadband output load network of the final stage PA and broadband Elliptical harmonic
filter [58], [76]. This technique flattens the load angle of the output load network while providing high
11
Harmonic suppression of two-way radio applications needs typical 73 dBc (second and higher order harmonics) for VHF/UHF
bands.
12
First, second and final stage transistors are employed HBT (ADA4734 from Avago Inc.), LDMOS (RD01MUS1 from Mitsubishi)
and LDMOS (RD07MVS1 from Mitsubishi), respectively.
11
harmonic suppression for wide frequency range. In a comparable work, [59] – [60] have demonstrated
improvement over second harmonics suppression.
The concept is validated experimentally, and a prototype board of the multi-stage broadband PA is shown
in Figure 2.10. The PCB (FR-4 material) has a dielectric εr of 4.5 and a thickness h of 14 mils. The
summary measured results are given in Table 2.5.
Figure 2.10: Photograph of prototype board of broadband parallel-circuit Class E PA with
reactance compensation technique.
Parameters
Performance
Operating Bandwidth (MHz)
134 – 174
Output Power (W)
6.5
Efficiency (%)
>65
Power Flatness (dB)
± 0.9
Stability with 10:1 VSWR
Stable
Harmonic level
>73 dBc
Table 2.5: Summarized measurement results of the multi-stage broadband PA [20].
2.5 Balanced amplifier (BA)
BA is different compared to push pull configuration. A balun transforms a balanced system that is
symmetrical (with respect to ground) to an unbalanced system with one side grounded [62]. Figure 2.11
shows a balanced configuration consisting of pair of transistor and two baluns. The design offers other
advantages where the baluns and associated matching circuit have greater bandwidth, lower loses and
reduced even-harmonic levels. These includes better power added efficiency, reflections are absorbed in
passive combiner terminations, improving input and output matching as well as stability and individual
transistor can be optimized for gain flatness.
12
−
Vi1
+
+
Vo1
RF in
RFout
Balun
+
Vi2
Balun
−
−
Vo2
Figure 2.11: Basic BA configuration.
The input signal which is fed to the balun is split into two signals with equal amplitude and 180º out of
phase to the gate of the transistor [63]. The output signals from the drains of the transistors which are
equal but 180º out of phase are combined at the output of the balun. As can been seen in Figure 2.11, the
input voltages applied to th gates can be described as Vi1 = Vm cos ωt and Vi2 = -Vm cos ωt. The output
voltages Vo1 and Vo2 can be expressed as power series expansion of Vi1 and Vi2 [63], which yields
V o 1 = A o + A 1 cos ω t + A 2 cos 2 ω t + A 3 cos 3 ω t + ... ,
(2.15)
V o 2 = A o − A 1 cos ω t + A 2 cos 2 ω t − A 3 cos 3 ω t + ... ,
(2.16)
where A’s are constant. Total output voltage Vo is proportional to the difference between (2.15) and
(2.16), therefore contain only odd-order terms. This condition proves that the circuit will balance out all
even order harmonics in the output. In addition to the fact that output voltage contains no even-order
harmonics, the balanced configuration possesses “half wave” or “mirror” symmetry, which implies that the
bottom half of the amplifier, when shifted to 180º along the axis, will be the mirror image of the top half.
Recent state-of-art of high efficiency design methodology for BA with various device technologies are
reported in [64] - [66]. However, this work explains the design procedure to achieve broadband
performance using load pull technique to obtain input and output networks impedance [67].
A test board using Rogers material was fabricated, where dielectric constant εr of 3.4 and thickness h of
30 mils. Input and output impedance matching are based on parallel-coupled line transforming from lower
impedance of the device. Figure 2.12 shows the photograph of BA, and summary measured results are
given in Table 2.6
+Vg1
+Vd1
RFout
RFin
Input matching
network
Output matching
network
+Vd2
+Vg2
Figure 2.12: Photograph of prototype board of BA.
13
Parameters
Performance
Operating Bandwidth (MHz)
940-1100
Output Power (W)
0.8
Efficiency (%)
30
Power Flatness (dB)
1.1
Gain (dB)
12
Table 2.6: Summarized measurement results of the BA [67].
2.6 Unified Broadband Matching Approach
Ideally, the designer requires the transfer of the available power from the generator to the load, this in
turn requires a flat transducer power gain characteristic in the band of operation at a unitary gain level
with a sharp rectangular roll-off [68], as illustrated in Figure 2.13. However, the achievement permits the
ideal power transfer at only a single frequency. In this case, the matching network is matched in
conjugation with the generator impedance. Therefore, the design of a matching network over a wide
frequency range with high and flat gain characteristics presents a very complicated theoretical problem. It
is well known that the terminating impedances and impose the possible highest flat gain level over entire
frequency band i.e. the theoretical gain-bandwidth limitation of the matched system [69].
T(ω)
T0
ω1
ω2
Figure 2.13: Ideal form of the transducer power gain over the specified frequency bandwidth.
It should be mentioned that the filter or the insertion loss problem might also be considered as a special
form of the broadband matching problem that deals with a resistive generator and a resistive load, see
Figure 2.14. In this respect, well-established filter design techniques may be employed for broadband
matching problems where appropriate. There are two main approaches to the solution of broadband
matching problems, namely analytical and computer-aided solutions. The classical procedure is through
analytical gain-bandwidth theory [70]. The second type technique after Carlin [71]. In principle, both
approaches seek optimal achievement of the maximum level of minimum transducer gain within the
passband. Analytical gain-bandwidth theory is essential to understand the nature of the matching
problem, but in general it is not accessible beyond simple problems. The real frequency computer-aided
13
solutions , however, are rather practical and easy to carry out for more complicated problems.
Generally, the lossless matching network can be described in terms of two-port parameters (i.e.
impedance, admittance, chain, real or complex, scaterring or transmission parameters) or by means of
the driving point that is so-called Darlington immitance or bounded real reflection coefficient [69].
Darlington’s theorem states that any positive real immitance or bounded reflection coefficient can be
realized as a lossless two-port terminated with resistive part, and the Darlington equivalent is shown in
Figure 2.15.
13
Real frequency technique is semi-analytical approach, requires computer-aided solution [26].
14
+
RG
Filter
RL
-
Figure 2.14: Typical diagram illustrating filter or insertion loss problem.
Lossless
two-port
1
Z, S
Figure 2.15: Darlington equivalent of a driving point impedance Z or reflection S.
Based on the fundamental gain-bandwidth theory introduced by Bode [70], the analytical approach to
14
single matching problem
was first developed by Fano [71] using the Darlington equivalent of the
passive load impedance ZL. Later Youla [72] proposed rigorous solution to the problem using the concept
15
of complex normalization. In order to solve double matching problem , Youla described the lossless
matching network in terms of complex normalized scattering parameters with respect to
frequency-dependent impedances of generator and load terminations [72]. The complete analytic solution
to the double matching problem has been accomplished by Yarman and Carlin [73], which relates to the
real and complex normalized generator and load reflection coefficients of the doubly matched system.
Instructional account of the gain-bandwidth theory for both single and double matching problems has
been elaborated by Chen [74]. In end of Chapter 6, semi analytical with real frequency computer-aided
technique by means of Darlington theorem is used to design broadband matching network [26].
2.7 Conclusion
Basic bandwidth limitation analysis of a single ended PA device is discussed. Device selection and circuit
design are essential to achieve broadband frequency response. One should bear in mind that for high
power broadband amplifier requirements, a low-fτ power transistor, and large device periphery must be
considered to achieve output impedance close to 50 Ω. Consequently, stringent input matching is needed
to compensate large Cgs, and this reduces operating gain. However, the gain can be improved with proper
circuit design.
Various broadband design techniques including broadband switched mode PA, linear and efficient PA,
multi-stage PA, and BA are demonstrated. These amplifiers demonstrated state-of-art power performance
of broadband VHF/UHF frequency range. These works give an understanding of power performance over
wide bandwidth, before begin of DA works. Next chapter will review the DA theoretical concept and
analysis in details.
14
Single matching: This is a matching problem where one of the passive terminations of the network is resistive, whereas the other
is complex or frequency dependent [68].
15
Double matching: This is matching problem where both passive terminations of the network are complex [68].
15
Chapter 3.
Distributed Amplification Concept and Practical
Distributed Amplifiers Design methodology
The concept of traveling wave or distributed amplification has been around forr over half a century. The
term distributed amplifier (DA) was originated in a paper by Ginzton in 1948 [77]. However, the underlying
concepts can be traced back to a patent by Percival in 1937 [78]. DAs employ a topology in which the
gain stages are connected such that their capacitances are isolated, yet the output currents still combine
in an additive fashion. Series-inductive elements are used to separate capacitances at the input and
output of adjacent gain stages. The resulting topology, given by the interlaying series inductors and shunt
capacitances, forms a lumped components artificial transmission line. The additive nature of the gain
dictates a relatively low gain, and however the distributed nature of the capacitance allows the amplifier to
achieve very wide bandwidths, in Figure 3.1.
This chapter discusses on the distributed amplification concept and theoretical analysis i.e. Beyer model
[4], Niclas model [6] and McKay model [29]. At the end of the chapter, practical design methodology of
DA is given which lead to systematic approach to design DAs.
Ld/2
Ld
Ld
Ld
Ld/2
Zdt
Vout
Lg/2
Lg
Lg
Vin
Lg
Lg/2
Zgt
Figure 3.1: Basic topology of DA. Lg and Ld are denote gate and drain line, respectively. Vin is the
input signal feeding, and Vout is output voltage [28].
3.1 Concept of Distributed Amplification
3.1.1
Introduction
Gain and bandwidth products of an amplifier stage limited by intrinsic parameters to the active device
employed, expanding the bandwidth will give rise to a reduction in the gain [28]. As the gain is made
close to unity, it becomes inefficient to cascade amplifier stages. On the other hand, combining the
outputs from a number of active devices in parallel will increase the output power but will produce no
improvement in the gain bandwidth product [4]. The solution is to find an arrangement in such a way that
the output currents from a number of devices are superimposed constructively while effects of the shunt
capacitances are not accumulated, and this is the base of distributed amplification [4].
Transistor’s input and output capacitance as part of the lumped elements of an artificial transmission line,
formed with the series inductance that connects adjacent drains and gates. A schematic of a DA is shown
in Figure 3.2. Signal is coupled from the gate line to the drain line through transistors. The transmission
lines can be of either the artificial type, i.e. made up of discrete-elements inductors, or transmissions lines
16
(i.e. microstrip or coplanar). The distributed amplifier concept has been successfully applied to monolithic
GaAs MESFET amplifiers at microwave frequencies in the 80’s for larger gain-bandwidth products [5].
Ayasli et al. have published design formulas for the gain of traveling wave amplifier based on an
approach that approximates gate and drain lines as continuous structures [79]. Similarly, Beyer et al.
developed a closed form expression for the gain that depends on the circuit propagation constants and
the gate circuit cut-off frequency [4]. Niclas et al. have also developed a method based on the use of the
admittance matrix employing the Y parameters of the transistor model in an amplifier with either artificial
or real transmission lines [6]. This method allows the use of much more sophisticated model for the
transistor developed from its measured S-parameters [80]. McKay et al. also proposed a formulation
based on a normalized transmission using matrix formulation [29].
The operation of the DA can be explained referring to Figure 3.2, where a RF signal applied to the input
port of the gate line travels down the line to the termination where it is absorbed. The traveling signal is
picked up by the gates of the individual transistor and transferred to the drain line via their
transconductances gm. If the phase velocities on the gate and the drain lines are identical, the signals on
the drain line add in the forward direction [4]. The phase velocities between gate and drain lines can be
synchronized simply by setting the gate and drain line cut-off frequencies identical. Any signal which
travels backward and is not entirely canceled by the out of phase additions will be absorbed by the drain
line termination [4].
The concept of distributed amplification is based on combining the input and output capacitances of the
actives device with inductors in such a way that two artificial transmission lines are obtained. The input
and output capacitance of each device becomes the capacitance per unit section for these lines
(Figure 3.3) and the lines are coupled by the gm of the active device. As a result, it is possible to obtain
amplification over a wider bandwidth than with conventional amplifiers [28]. Designers have concentrated
mainly on increasing the gain-bandwidth product and the gain flatness, as well as on output power
capabilities. In DA, the transmission structures employed are often analyzed as a cascade of two ports,
as we will see in the following section. For the amplifiers employing transmission lines, the voltage
developed along the output line tends to increase as the cut-off frequency is approached if the
magnitudes of the current injected by active devices along the line remain constant [28]. This is the result
of the factor of (1-ω2/ωc2)-1/2 in Zoπ, the mid-shunt image impedance.
Vdrain
Drain line
Output
Zd
Vgate
Input
Zg
Gate line
Figure 3.2: The distributed amplification concept.
17
Lg/2
Lg/2
Lg/2
Lg/2
Cgs
Rgs
Cgs
Rgs
(b)
(a)
Figure 3.3: Lossless elementary section of DA a) gate line b) drain line.
3.1.2
Image impedance method
The image parameter method applied to DA since it consists of a cascade of identical two-port networks
forming an artificial transmission line. The analysis can be conveniently accomplished using the ABCD
parameters, because the overall ABCD matrix is the product of those of the cascaded two-ports [28] (as
shown in Figure 3.4).
I1
V1
I2
Q
V2
Figure 3.4: A two-port network.
When considering signal transmission and impedance matching in cascaded two-ports, each two-port
should operate with the appropriate impedance terminations so that the maximum power transfer takes
place over the prescribed bandwidth. Such condition can be met by terminating the two-port with a pair of
impedances known as image impedances so that the impedance appears the same when one looks into
either direction of each port as shown in Figure 3.5. The impedances as Zi1 and Zi2 can be expressed as
Z i1 = Z sc1Z oc1 =
B A,
DC
(3.1)
Z i 2 = Z sc 2 Z oc 2 =
BD,
AC
(3.2)
18
where Zsc1 and Zoc1 are the impedances appearing at port 1, with port 2 short circuited and open circuited,
respectively, and likewise for Zi2 . If the network is symmetrical, Zi1 and Zi2 become identical, known as
characteristic impedance and is denoted Z0.
Q
Zi 2
Zi1
(a)
Q
Zi1
Zi2
(b)
Figure 3.5: A two-port network terminated by its image impedance.
Figure 3.6 shows the case of an infinite number of identical networks connected so that at each junction
is connected together. Due to the way the infinite chain of networks is connected in Figure 3.6, the
impedances seen looking left and right at each junction are always equal, hence there is never any
reflection of a wave passing through a junction. Thus, from the wave point of view, the networks of the
figure are perfectly matched [28]. The image impedance Zi for a reciprocal symmetric two-port is defined
as the impedance looking into port 1 or 2 of the two-port when the other terminal is also terminated in
Zi [28]. To achieve an impedance match over a broad range, the load and source impedance must be
transformed into the image impedance. Otherwise, the gain response will not be flat as a function of
frequency.
Zi 1
I1
I2
1 Q1 2
Vin
Zi1
IN
1 QN 2
2 Q2 1
Zi1
Zi2
Zi2
Zi2
Figure 3.6: Artificial transmission line.
Having obtained expressions of the image impedance for a reciprocal two-port, we now apply them to a
number of elementary filter sections often found in distributed amplifiers. A simple filter can be
19
constructed from two circuit elements as shown in Figure 3.7, known as L section or half section. The
image impedances at port 1 and 2 are referred to as Zi1 and Zi2, respectively, because they are also the
characteristics impedances of the T network and π network formed by cascading two identical L sections
in a back-to-back fashion. From (3.1) and (3.2), we obtain
Z OT =
ω2
L
(1 − 2 ) ,
C
ωc
(3.3)
L
ω 2 −1
=
(1 − 2 )
C
ωc
(3.4)
where ω c = 2 / LC ,
(3.5)
ZOπ
ωc known as the cut-off frequency, is the frequency where the image impedances go from real to
imaginary.
If the desired characteristics impedance Z0 of the transmission line is fixed, the cut-off frequency, fc can
be expressed as
fc =
1
.
π ⋅C ⋅ Z0
(3.6)
(3.6) shows that the bandwidth of a DA decreases as value of the capacitance, C increases (in reality, C
is referring to Cgs and Cds). Since this capacitance is proportional to the dimension of the employed
transistors and the gain of the DA, (2.6) also shows possible tradeoff between gain and bandwidth in DA
design.
L/2
C/2
ZOT
ZOπ
Figure 3.7: A low pass L section by means of constant-k image impedance.
3.2 Theoretical Analysis of DA
Analysis of DAs is facilitated by the assumption of lossless transmission networks which are realized from
ladder networks based on constant-k low pass filters, and unilateral active devices [28]. A simplified
equivalent circuit of the transistor 16 is shown in Figure 3.8. Rgs, Cgs, Rds, and Cds are the gate to source
16
In most DA works, simplified transistor model excluded the feedback effect Cgd, due to the fact the analysis becomes more
complex. Furthermore, this method gives freedom to isolate the gate and drain to form effective artificial transmission line by means
of constant-k ladder network.
20
and drain to source resistance and capacitance, respectively, gm is the device trans-conductance. Next
subsection will give us a detail analysis of DA in different approach models.
Drain
Gate
Cgs
gmVgs
Vgs
Cds
Rds
Rgs
Source
Figure 3.8: Simplified small signal circuit model of a transistor.
3.2.1
Analytical approach of Beyer model (Two-port theory)
As given [4], the device is considered unilateral i.e. Cgd (the gate to drain capacitance) is neglected. The
equivalent gate and drain transmission lines are shown in Figure 3.9 (a) and Figure 3.9 (b). The lines are
assumed to be terminated by their image impedances at both ends. With the unilateral device model
employed, the two transmission lines are non-reciprocally coupled through the action of the
trans-conductance gm. From Figure 3.9 (b), the current delivered to the load [4] is given as
n
1
⎤
−γ d / 2 ⎡
I 0 = g me
Vk e− ( n − k )γ d ⎥ ,
∑
⎢
2
⎣ k =1
⎦
(3.7)
where Vk is the voltage across Cgs of the k-th transistor and γd =αd + jβd is the propagation factor of the
drain line, αd and βd are the attenuation and phase shift per section on the drain line, n is the number of
transistors in the amplifier. Vk can be expressed in terms of the voltage at the gate terminal of the k-th
FET [4] as
Vk =
Vi e
− ( 2 k −1) γ g / 2 − j tan −1 (ω / ω g )
⎡ ⎛ω
⎢1 + ⎜
⎢ ⎜⎝ ω g
⎣
1/ 2
⎞
⎟
⎟
⎠
⎡ ⎛ ω ⎞2 ⎤ ⎤
⎢1 − ⎜⎜ ⎟⎟ ⎥ ⎥
⎢⎣ ⎝ ωc ⎠ ⎥⎦ ⎥⎦
,
(3.8)
where Vi is the voltage at the input terminal of the amplifier and γg = αg + jβg is the propagation factor of
the gate line. αg and βg are the attenuation and phase shift per section on the gate line, ωg = 1/(RgsCgs) is
the gate circuit cut-off frequency, and ωc = 2πfc is the cut-off frequency of the lines (fc = 1/LgCgs). For
constant-k type transmission lines, the phase velocity is a well-known function of the cut-off frequency ωc
21
of the line. By requiring gate and drain lines to have the same cutoff frequency, the phase velocities are
constrained to be equal. Therefore, we have βg = βd = β. Then, I0 [4] can be expressed as
⎡n
⎤ − n (α −α ) / 2 − jnβ − j tan −1 (ω / ω g
g mVi sinh ⎢ (α d − α g )⎥ e d g e
)
2
⎣
⎦
I0 =
.
1/ 2
⎡ ⎛ ω ⎞2 ⎤ ⎡ ⎛ ω ⎞2 ⎤
⎡1
⎤
2⎢1 + ⎜ ⎟ ⎥ ⎢1 − ⎜ ⎟ ⎥ sinh ⎢ (α d − α g )⎥
⎜
⎟
⎜
⎟
⎢ ⎝ ωg ⎠ ⎥ ⎢ ⎝ ωg ⎠ ⎥
⎣2
⎦
⎣
⎦ ⎣
⎦
(3.9)
The power delivered to the load and input power to the amplifier are given, respectively, by
2
P0 = I 0 ℜ[ Z ID ] , and
Pi =
Vi
(3.10)
2
2 Z IG
2
ℜ[ Z IG ]
(3.11)
where ZID and ZIG are the image impedances of the drain and gate lines. Therefore, the power gain of the
amplifier is given as
GP =
g m 2 Z 0 g Z 0 d sinh 2 [0.5n(α d − α g )]e
⎡ ⎛ w
4 ⎢1 + ⎜
⎢ ⎜⎝ wg
⎣
where Z0g =
⎞
⎟
⎟
⎠
2
⎤⎡ ⎛ w
⎥ ⎢1 − ⎜
⎥ ⎢ ⎜⎝ wg
⎦⎣
⎞
⎟
⎟
⎠
2
−0.5 n (α g +α d )
⎤
⎥ sinh 2 ⎡ 1 (α d − α g )⎤
⎢⎣ 2
⎥⎦
⎥
⎦
,
(3.12)
Lg / C g and Z0d = Ld / Cd , are the characteristic impedances of the gate and drain line,
respectively.
The most commonly used definition of power transducer gain is the so-called transducer gain GT defined
as
GT =
Pload
,
Pav
(3.13)
where Pload is the power delivered to the load by the amplifier, and Pav is the power available from the
source. The latter is the same as the power delivered to the amplifier input by the source under the
condition that the amplifier input impedance is conjugate matched to the source impedance.
22
Lg/2
V1
Vin
Lg/2
Lg
Cgs
V2
Lg/2
Lg/2
Cgs
Cgs
Vn
Termination
Rgs
Rgs
Rgs
(a)
Ld/2
Ld/2
Ld
Ld/2
Ld/2
gmV2
gmV1
gmVn
Rds
Termination
Cds
Rds
Cds
ZLd
Rds
Cds
(b)
Vout
Load
Figure 3.9: (a) Gate transmission line and b) drain transmission line.
3.2.2
Analytical approach of Niclas model (Admittance matrix)
The elementary circuit of a lumped element DA can be represented by a four-port as shown in [6].
Replacing the transistor by its two-port representation with the current source ik leads to the equivalent
circuit shown in Figure 3.10. The matrix equation which relates the voltage and current in Figure 3.10
takes the following form as
⎡V Dk −1 ⎤
⎡VDk ⎤
⎢
⎥
⎢
⎥
I
⎢ Dk −1 ⎥ A ⎢− I Dk ⎥
⎢VGk −1 ⎥ = k ⎢VGk ⎥ ,
⎢
⎥
⎢
⎥
⎢⎣− I Gk ⎥⎦
⎣⎢ I Gk −1 ⎥⎦
(3.14)
where
Ak = A1k AFk A2 k .
(3.15)
[A1k] is the matrix of the input link and [A2k] is that of the output link as shown in Figure 3.10, while [AFK]
constitutes the transistor admittance matrix. Cascading n elementary circuits and terminating the idle
ports with RG and RD (the gate and drain loads respectively) yields the matrix equation [6],
23
⎡VDn
⎤
⎤
⎡VD 0
⎢
⎥
⎥
⎢
−1
−I
⎥
⎢− RD VD 0 ⎥ D ⎢ Dn
⎢VGn
⎥,
⎢V
⎥=
⎢
⎥
⎢ G0
⎥
⎢⎣ − RG −1VGn ⎥⎦
⎥⎦
⎢⎣ I G 0
(3.16)
where
k =0
D=
∏A
k
.
(3.17)
n
VD(K-1)
Input
Drain
Link
Output
Drain Link
IDK
ID(K-1)
-Y12
IG(K-1)
VG(K-1)
VDK
(Y22+Y12)
IGK
(Y11+Y12)
Input
Gate
Link
Output
Gate Link
VDK
Figure 3.10: Equivalent four-port representation of the circuit of DA form [6].
The insertion gain is expressed as the ratio of the signal power delivered to the load by the circuit to the
signal power delivered directly to that load. The insertion gain can now be determined after some
algebraic steps [6] as following
Gain = 2Y0
C2
,
C
(3.18)
with Y0 = 1 / Z 0 ,
(3.19)
−1
−1
C1 = D(4,3) + RG D(4,4) + Y0 ( D(3,3) + RD D(3,4) ,
(3.20)
24
C 2 = D ( 2,3) + RG −1 D (2,4) + Y0 ( D (1,3) + RD −1 D (1,4) ,
−1
(3.21)
−1
C = C1[ D (2,1) + Y0 D (2,2) + Y0 ( D(1,1) + RD D(1,2))]
−1
−1
− C2 [ D(4,1) + Y0 D(4,2) + Y0 (D(3,1) + RD D(3,2))] .
(3.22)
This equation represents the exact solution for the gain of a DA in its most general form. In the case of
the DA structure, where the load and the input impedance are the same, typically (50 Ω). The insertion
and the transducer gain define the same quantity.
3.2.3
Analytical approach of McKay model (Wave theory)
The normalized transmission matrix approach was presented by McKay et al. [29]. This theory applies to
a general class of distributed amplifier with discrete sampling points on the gate line which couple to
discrete excitation points on the drain line. Si Moussa et al. [81] extend this concept by considering the
bilateral case obtained by including the gate-drain capacitance Cgd of the transistor. Using the scattering
formalism, the wave quantities [29] as shown in Figure 3.11 are given by:
b±n =
Vbn
Z 0d
a±n =
Van
Z0g
± ibn Z 0 d ,
(3.23)
± ian Z 0 g ,
(3.24)
where Van, ian, Vbn and ibn are the total voltages and currents at section n the ‘a’ and ‘b’ denote the
complex wave amplitudes on the gate and the drain line, respectively. Z0g and Z0d are the characteristic
impedances of the gate and drain line, respectively. It is the last equation that allows making the analysis
of the bilateral case [29].
The transfer matrix [M] defined as [M] = [G−1/2][T]N[G1/2], [29] is given by
[ ]
Wout = [G −1 / 2 ] T N [G1 / 2 ]Win ,
+
+
−
(3.25)
−
T
where Wi = [ ai bi ai bi ] ,
(3.26)
where T denotes the operator transpose, (in) and (out) are the input and the output vector [84],
respectively.
[G1 / 2 ] = diag{exp( −θ g / 2), exp(−θ d / 2), exp(θ g / 2), exp(θ d / 2)} = [G−1 / 2 ]−1 .
(3.27)
Note that the propagation constants θg and θd of, respectively, the gate and the drain line, are complex.
[T ] = [G ][ H ] ,
(3.28)
25
where [G ] = diag{exp( −θ g ), exp( −θ d ), exp(θ g ), exp(θ d )} ,
⎡
1 + jZ 0 g C gd ω
⎢
⎢
1
⎢ H + jC gd ω Z 0 g Z 0 d
2
[H ] = ⎢
1
⎢
− jZ 0 g C gd ω
⎢
2
⎢
1
⎢− H − jC gd ω Z 0 g Z 0 d
2
⎣
where H = −
1
jC gd ω Z 0 g Z 0 d
2
1
1 − jZ 0 d ZC gd ω
2
1
jC gd ω Z 0 g Z 0 d
2
1
jZ 0 d C gd ω
2
(3.29)
1
jZ 0 g C gd ω
2
1
− H − jC gd ω Z 0 g Z 0 d
2
−
1 − jZ 0 g C gd ω
−H −
1
jC gd ω Z 0 g Z 0 d
2
1
jC gd ω Z 0 g Z 0 d
2
1
− jZ 0 d C gd ω
2
1
jC gd ω Z 0 g Z 0 d
2
1
1 + jZ 0 d C gd ω
2
−
⎤
⎥
⎥
⎥,
⎥
⎥
⎥
⎥
⎥
⎦
1
g m D (ω ) Z 0 g Z 0 d ,
2
ω is the pulsation and D(ω ) =
(3.31)
1
.
1 + jR gs C gsω
(3.32)
b+n
Drain
line
b+n+1
b-n
Zod
(3.30)
ibn
b
Zod
b-n+1
ibn+1
Zod
Vbn+1
Vbn
Zod
Cgd
a+n
i’
a+n+1
a’-n
a-n
G
Generator
a-n+1
ian
ian+1
Zog
Van
Gate line
Van+1
a
Zog
Zog
Voltage sampler
Figure 3.11: Elementary section of bilateral distributed amplifier. The variables bn and an represent
scattering waves [29].
Under the assumption of perfect matching at the input and output lines, the transmission coefficient S21
which relates the incident gate at the input to the incident drain signal at the output, has the following form
26
S 21 =
b + out
ain
(3.33)
where b+out is the output wave of the last section on the drain line and ain is the input wave of the first
section of the gate line [84].
3.3 Gain/ Power-bandwidth trade-off
The transfer characteristics of an amplifier with lumped components as the coupling elements will reveal
that the gain and the bandwidth cannot be simultaneously increased beyond a certain limit. As a result,
these two quantities are often considered trade-offs in the design of an amplifier. To begin the
understanding the trade-offs, lets consider a simple bandpass amplifier consisting of an active device as
shown in Figure 3.12. The voltage transfer function [28] is given as
Av (ω ) =
− gmR
ω ω
1 + jQ ( − 0 )
ω0 ω
,
(3.34)
where ω0 = 1/ and Q = ω0RC.The maximum gain occurs at midband and has a magnitude of gmR. The
bandwidth (-3 dB) BW = ω0/2πQ or 1/2πRC [28]. Hence, the gain-bandwidth product of the amplifier is
Av 0 BW =
gm .
2πC
(3.35)
It is clear from (3.35) that the gain-bandwidth product is proportional to gm/C. The R which influences the
maximum gain in the passband, does not appear in the gain-bandwidth product. From a device point of
view, the gain-bandwidth product can be explained (where L can be eliminated Figure 3.12). The amplifier
has a maximum gain of –gm/R at DC, and a bandwidth of 1/2πRC, so (3.35) is still valid in this case.
Hence, the gain-bandwidth product cannot be overcome by connecting in parallel configuration.
Vin
gmVin
R
L
C
Vout
Figure 3.12: A simple bandpass amplifier schematic.
In DA, the parasitic capacitance (shunted) of the device is well-isolated from the device to form low-pass
filtering response with the transmission line inductance, where wide bandwidth is promising. To explain
gain-bandwidth product in DA, Figure 3.9 will be reviewed. Voltage gain of the DA [4] can be shown to
A =
g m ( Z 0 g Z 0 d )1/ 2 sinh[0.5n(α d − α g )]e
⎡ ⎛ w
2 ⎢1 + ⎜
⎢ ⎜⎝ wg
⎣
⎞
⎟
⎟
⎠
2 1/ 2
⎤
⎥
⎥
⎦
⎡ ⎛ w
⎢1 − ⎜
⎢ ⎜⎝ wg
⎣
⎞
⎟
⎟
⎠
2 1/ 2
⎤
⎥
⎥
⎦
−0.5 n (α g +α d )
.
⎤
⎡1
sinh ⎢ (α d − α g )⎥
⎦
⎣2
27
(3.36)
From (3.36), one can show that the number of the devices which maximizes gain at any given frequency
is
nopt =
ln(α d / α g )
αd − α g
.
(3.37)
Podgorski and Wei [110] have shown for the optimum gate-width of a traveling wave amplifier has similar
relation to the (3.37). Therefore, it is clear that in presence of attenuation, the gain of a DA cannot be
increased indefinitely by adding devices [4]. Additional transistors not only decrease the excitation of the
last device but also increase the overall attenuation on the drain line. αg and αd are gate and drain line
attenuation [28], respectively, given by
αg =
αd =
(ω / ω c ) 2 (ω c / ω g )
(
)
,
(3.38)
1 − 1 − (ω c / ω g ) 2 (ω / ω c )
(ω d / ω c )
,
1 − ω 2 / ωc
(3.39)
2
where ωg is gate corner frequency, given by 1/RgsCgs and ωd is drain corner frequency, given by 1/RdsCds.
[4] showed that by extending analysis from [106], (3.38) and (3.39) can be rearranged as
αg =
αd =
2aX k
2
,
(3.40)
⎡ 4a
⎤ 2
n 1 + ⎢ 2 − 1⎥ X k
⎣n
⎦
2
2b
,
n 1− Xk
(3.41)
2
nω d
where a = nω c , b =
and Xk = ω/ωc.
2ω g
2ω c
At DC, (3.36), after substituting (3.40) and (3.41) can be rewritten as
A0 =
g m ( Z 0 g Z 0 d )1/ 2 sinh(b)e − b
.
(3.42)
2 sinh(b / n)
To explain the trade-off between gain and bandwidth of DA, voltage gain from (3.36) can be used.
Normalizing the voltage gain to DC operation is convenient to understand the gain and bandwidth tradeoff. The term a and b are used to simplify the normalized gain.
28
Normalized gain A/A0 can be deduced from (3.36) and (3.42), and the expression shown as
1/ 2
⎡
⎞ 2 ⎤ ⎤ −[ b /(1− X k 2 )1 / 2 +aX k 2 /[1+( 4 a 2 / n2 −1) X k 2 ]1 / 2
⎛ 4a 2
b b
2 1/ 2
2 ⎡
sinh( )e sinh ⎢b /(1 − X k ) − aX k / ⎢1 + ⎜⎜ 2 − 1⎟⎟ X k ⎥ ⎥ e
n
⎢
⎠
⎦ ⎥⎦
⎣ ⎝ n
⎣
.
AN = A / A0 =
1/ 2
1/ 2
2
2
⎡
⎤
⎡ 4a
⎞ 2⎤
⎛ 4a
1
2⎤
2 1/ 2
2
2 ⎡
sinh(b) ⎢1 + 2 X k ⎥ 1 − X k
sinh ⎢b /(1 − X k )1/ 2 − aX k / ⎢1 + ⎜⎜ 2 − 1⎟⎟ X k ⎥ ⎥
n
n⎢
⎣
⎦
⎠
⎦ ⎥⎦
⎣ ⎝ n
⎣
[
]
(3.43)
Normalized gain (3.43) over frequency response Xk for various a and b are illustrated in Figure 3.13. n of
4 is selected to understand the gain-bandwidth trade-off for few case a and b. Important point to be noted
is beyond n = 4, the gain response degraded for same a and b. Nevertheless, lower a and b value
selection lead to broadband frequency response, as shown in Figure 3.13. For an example, with selection
a = 1 has poorer bandwidth response than that a = 0.6. Therefore, it is important to select a device having
suitable ωg and ωd, for wideband operation.
a=0.6, b=0.14
a=0.7, b=0.24
AN
a=0.8, b=0.4
a=1, b=0.6
Xk
Figure 3.13: Normalized gain over frequency response for various selection of a, b and n = 4.
Non-uniform DA design applying drain line impedance tapered eliminating drain-line reverse wave and
maximizing output power combination [16]. Consider a non-uniform DA (refer to Figure 3.14) with cut-off
frequency ωc, gate-line characteristic impedance ZG, and maximum output power Pmax consisting of n
sections and having transistors with maximum power Po and gate-source capacitance Cgs. Its output
power-bandwidth product (PBW) [16] is defined by
1
n ⋅ (Vbk − Vk )
,
⋅
8 ⋅ ZD
π ⋅ Z G ⋅ C gs
2
PBW = Pmax ⋅ f c = n ⋅ Po ⋅ f c =
(3.44)
where ZD load presented to its drain terminal, Vbk and Vk are break-down and knee voltage, respectively.
29
Pmax = n.Po
Rg
gmvi Cds Rds
Cg
n section
Po
s
Gp
Common-source FET
Pin(max)
Figure 3.14: Maximum transistor output is given by Gp⋅Pin(max) for non-uniform DA.
(Vbk – Vk)/Cgs ratio, which is typically fixed value, Po depends on Vbk and Vk, which along with Cgs,
increases with gate length. Po is mainly contributed from the power transistor. However, for moderate
bandwidth operation i.e. 2 GHz, higher Pmax could be achieved.
The increased single stage gain permits a proportional Pmax increase in those amplifiers limited by
dynamic (linear) range of the input signal [16]. The maximum transistor output power Po is given by
Gp⋅Pin(max), which is proportional to the single stage amplifier power gain Gp and to the maximum limited
input strength Pin(max). Therefore, connecting few stages of non-identical transistors with inter-stage
tapered impedance can increase Pin(max) to the power transistor, and having high-fτ transistor (lower Cgs)
can be coupled to the gate line [14], as given in Figure 3.15.
To gate
line
Q1
M1
Qn
MN
Power
transistor
To drain
line
Figure 3.15: Connecting few stages of non-identical transistors with inter-stage tapered
impedance (broadband matching networks e.g. M1,..,M2) can increase Pin(max) to the power
transistor, and having high-fτ transistor (lowest Cgs) can be coupled to the gate line input. Q1,..,QN
are high-fτ transistors.
As given in (3.44), n sections will increase the PBW products. However, adding more n sections will not
improve the products because of the losses associated with active transistor resistances. Beyer et al.
have showed that gain in conventional DA cannot be increased indefinitely by adding more sections [4].
In the following work will lead to determine an optimum n sections to maximize output power at a given
frequency associated with device input and output corner frequency. Output power of a DA is given by
2
Pmax
2 − n (α +α )
g m Vin e g d
=
2
2
(1 + ω 2 / ω g )(1 − ω 2 / ωc )
⎡n
⎤
sinh 2 ⎢ (α g − α d )⎥
2
⎣
⎦,
⎤
2 ⎡1
sinh ⎢ (α g + α d )⎥
⎣2
⎦
(3.45)
where αg and αd are gate and drain line attenuation, given in (3.38) and (3.39), respectively [4].and ωg is
gate corner frequency, given by 1/RgsCgs and ωd is drain corner frequency, given by 1/RdsCds. αg and αd
are the critical factor controlling the frequency response. The plot of αg and αd for GaN power transistor,
respectively are shown in Figure 3.16. The information of ωg and ωd, respectively of the power transistor
can be computed from the intrinsic elements. It is strongly evident from Figure 3.16 that the gate line is
more sensitive to frequency response than drain line attenuation, and the drain line attenuation does not
vanish at low frequency limit. Therefore, the sensitivity of the DA frequency response can be minimized
30
as the signal move towards ωc by coupling a high-fτ transistor to the gate line that is having high ωg. To
improve drain line attenuation, it is necessary that compensation network to introduce to an output of the
power transistor. Typically bigger device periphery causes the loading effect becoming stronger.
Attenuation compensation with an active load to reduce drain line losses dominated by Rds (drain-source
resistance) [82] is a common technique, but the cost and area are increases.
Number of section which maximizes output power given in [21] as
nopt
⎡ 3α − α g ⎤
ln ⎢ d
⎥
⎢⎣ 3α g − α d ⎥⎦ ,
=
αd − α g
(3.46)
Attenuation [Np]
Referring to [21], for larger device periphery (i.e. GaN device having gate-width of 3.6 mm), and to deliver
30 W from each device, nopt is approximately 3…4. To understand the trade-off relation between output
power and bandwidth, (3.45) can be plotted for various ωg and ωd .
Freq [MHz]
Figure 3.16: αg (red color) and αd (blue color) of the GaN power transistor. The αg and αd of the
transistor are computed from the intrinsic elements, Table 3.1.
Additionally from (3.44) by reducing ZD would benefit the products. The following section will explain the
optimum impedance that will be synthesized when ZD is reduced. Consequently, wideband impedance
transformation is required. One should bear in mind that by simplify reducing ZD will not guarantee the
multi-sources current source combining to a single load due to the fact that an optimum virtual impedance
in two directions i.e. Zu(k) and Zr(k) are not fulfilled (this will be discussed in section 4.2). Nevertheless, this
can be achieved and detail explanations will be given in Chapter 4.
3.4 Design Methodology of Practical DA
This section explains on design methodology of practical DA, including few steps from design
goal/specifications, device selection, analytical approach, and so on. These steps are applied in the DA
development throughout the thesis work, and experimentally demonstrated good performance without
any tuning in board level, especially significant for high power development (Chapter 6).
31
•
Design goal/specifications
Understanding the design goals/specifications is the first step to get started with DA design. The basic
design requirement of this work is to achieve high output power (Pout >10 W) DA to meet SDR
17
applications . Knowing the basic goal is Pout >10 W, break-down voltage Vbk can be computed from
Vbk − Vk = 8Pout RL ,
(3.47)
where Vk and RL are knee voltage and load impedance, respectively.
•
Device selection
If Vk in (3.47) is neglected (or assumed zero for simplicity), then Vbk over Pout can be computed with
condition RL = 50 Ω (to eliminate impedance transformation), and plotted in Figure 3.17. To achieve 10 W
or more, at 50 Ω impedance, the device must has Vbk at least 70 V (from Figure 3.17). Due to power
requirements and limiting operating voltage at 50 Ω condition, LDMOS and HBT devices are not suitable.
However, this can be achieved with RL <50 Ω impedance, where additional impedance transformation
network is required. Due to high bandgap, GaN HEMT device is selected as power device. The device
from CREE Inc. (part number of CGH40010F) offers Vbk of ~70 V with 50 Ω condition, which found to be
suitable for this application. However, the are many GaN device available from other device
manufacturers e.g. Nixtonic Inc., Fujitsu Inc., NXP Inc., etc.
•
Theoretical analysis (zero-order analysis)
Four new topologies are proposed in this thesis, and it is essential to understand the electrical
performance of the topologies. Therefore, the circuit analysis is begins with simplified FET (Field Effect
Transistor) model. The intrinsic elements of the small-signal FET model i.e. gm, Cgs, Cds, Rgs, Rds, etc are
18
extracted by means of device modeling , shown in Figure 3.18. For simplicity, feedback element Cgd is
neglected. It is convenient to investigate gate and drain lines independently to understand its
performance over the frequency range. Basic theoretical approach i.e. Superposition, Thevenin,
Darlington theorem, etc are employed in this thesis. As an example, in Chapter 4, generalized design
equation of virtual impedance by means of current source properties and simplified FET model are
developed. This provides a good initial guess of the circuit elements to begin with the next steps.
•
Analysis with VCCS and Cgd (first-order analysis)
As the next step, VCCS (Voltage Controlled Current Source) and Cgd are taken into consideration, as in
Figure 3.19, to understand the electrical performance of the proposed topologies. Due to the feedback
effect, the electrical performance would degrade and ripple may be expected near cut-off frequency fc.
Therefore, it is necessary to identify the circuitry elements that could compensate the electrical
degradation. Typically, gate and drain line impedances (including the dummy termination impedances)
are adjusted from the theoretical analysis in many DA applications. [83] showed the implementation of
non-uniform gate line can be employed in DA design to compensate degradation of electrical
performance
•
DC biasing circuitry design
DC biasing circuitry needs to be designed carefully because of the influence over the frequency
response. Figure 3.20 shows typical FET DC bias arrangement. DC feeding network, Ld together with Cd
selection must provide high impedance over the frequency bandwidth. Recommended value of Ld and Cd
17
This amplifier must meet RF parameters of two-way radio requirements e.g. output power, efficiency, stability, transient response,
etc, over frequency range over 40-2000 MHz.
18
All device modeling are performed by Modelithic Inc. under research contract with Motorola. However, as an exercise,
CGH40010F modeling is carried out at ITHE, RWTH Aachen. CGH40010F is high power packaged GaN device from CREE Inc.
32
19
20
for bandwidth operation from 10-2000 MHz is 180 nH and 33 pF , respectively [11]. As shown in [84],
multiple chokes and capacitors offer broadband response up to 3 GHz, refer to Figure 3.21. DC biasing
network: Lg and Cg must provide stable quiescent point.
Vbk [V]
F
Pout [W]
Figure 3.17: Break-down voltage Vbk vs. output power Pout for 50 Ω condition.
Gate
Drain
Rgs
+
vgs
-
Cgd
gmvgs Cds
Rds
Cgs
Figure 3.18: Simplified small-signal FET model.
Gate
Cgd
Drain
+
-
Figure 3.19: VCCS and Cgd of a single DA. Other intrinsic elements are included in the VCVS
section.
19
20
The high-Q ceramic 0603HP series chip inductors provided by Coilcraft Inc., and the Q up to ~150 at 1.7 GHz.
This is broadband high-Q capacitor 3060 size from Murata Inc, and details can be obtained at www.murata.com.
33
Some cases Lg is replaced with a resistor [11], and it provides transient controlled and stable operation.
Coupling capacitor Cb is necessary to block DC from flowing into RF path. With proper selection, it offers
broadband response, for instance 120 pF is adequate to satisfy up to ~2 GHz. Proper DC turn on
sequence is applied: first apply negative bias to the voltage (i.e. Vgate < 0 V) and then apply the drain
voltage (Vdrain > 0 V), and during turn off, Vdrain must be switched to 0 V and followed by Vgate.
Vdrain
Vgate
Cd
Cg
Ld
Lg
RFout
RFin
Cb
Q1
Cb
Figure 3.20: Basic FET DC bias arrangement.
Vdrain
Cd
R
Cd
L3
L2
Cb
L1
Cb
RFin
RFout
Figure 3.21: Broadband choke implementation given in [84].
•
Loading device into distributed output network
Generally in DA, output capacitance Cds becomes shunt element in a constant-k ladder network (refer to
Figure 3.22), and this determines the cut-off frequency fc of the line. Synthesizing the inductance required
careful consideration to provide desired impedance (with minimum flatness) over the frequency
bandwidth response. Loading properties of the line strictly rely on real part Rds, and significant loading
takes place with bigger size device periphery. Throughout Chapter 4 and Chapter 5, the DA prototype
boards are using medium power devices, and loading effect is not significant. However, in Chapter 6, due
to high power device, loading effect of the device is taken into considerations.
Due to packaged device implementation in the DA development, one should keep in mind to extract
effective real part and imaginary part of the input and output packaged device, Zin(ω) = Rin(ω) + jXin(ω)
34
and Zopt(ω) = Ropt(ω) + jXopt(ω), respectively. For an example, Figure 3.23 shows plot of S11 for a transistor
in packaged and die form of a medium power device [36]. It is important to note that resonance frequency
of a die is much higher than packaged device. Figure 3.24 (a) shows example of packaged properties of
the high power GaN device. Table 3.1 shows the extraction value of Zin(ω) and Zopt(ω) of high-fτ and
power transistors.
i1
Rds
Z0n
Z02
Z01
i2
Rds
i3
Rds
ZL
Figure 3.22: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω .
Z0i, i = 1, 2..n, referring to line impedance; consists of shunt capacitance and inductance. Note that
dummy termination is neglected to push all current to the load ZL.
Figure 3.23: S11 of a common emitter medium power device in packaged and die form [36].
As shown in Figure 3.24 (b), the optimum load impedance Ropt’ and Ropt (at both reference planes i.e. A
and B) are different, since package effects have to be taken into consideration. In practice, it is not
possible to observe the optimum RF voltage or current swing at reference A, but however, load pull
impedance contours of the device can be extracted at reference B. As aresult, Rds will be replaced with
Ropt(ω), and Xopt(ω) will be absorbed into the drain line to form desired ωc, as shown in Figure 3.25.
Therefore, the line inductance Li is realized by means of (3.48).
•
Synthesizing distributed input/output networks
Figure 3.25 shows when device loading into distributed output network. Therefore, with packaged device
selection, the cut-off frequency fc can be defined as
fc =
1
,
π LiCopt ,i
(3.48)
35
where Copt is the element extracted from the Xopt(ω), and Li is line inductance. In most cases, Copt < Cin,
where phase synchronization between gate and drain lines are achieved with capacitively coupled
technique [35], and the diagram of the technique is given in Figure 4.10.
Ca
Zin(ω) = Rin(ω) + jXin(ω)
La
Zout(ω) = Ropt(ω) + jXopt(ω)
La
Die
(a)
Package
Reference B, Ropt
Reference A, Ropt’
La
Cds
Rds
ZL
(b)
Figure 3.24: (a) Properties of high power GaN packaged device (CGH40010F) [85], and (b)
illustration of optimum load impedance Ropt’ (at reference A) and Ropt (at reference B).
first high-fτ transistor 21
second high-fτ
transistor 22
power transistor
(CGH40010F)
Rin
600 Ω
Cin
2.4 pF
Ropt
470 Ω
Copt
1.2 pF
378 Ω
3.3 pF
220 Ω
2.8 pF
102 Ω
5.9 pF
40 Ω
3.7 pF
Table 3.1: Extraction value of Zin(ω) and Zout(ω) of high-fτ transistor and power transistors. Note
that Rin and Cin in parallel form.
Once Zin(ω) and Zopt(ω) are identified, it is ready to synthesize the gate/drain line networks by means of
image impedance characteristics. One should bear in mind that selection of Copt from Xopt(ω) requires
careful analysis and valid below resonance frequency. Ropt(ω) only come into role for high power DA
design, and typically does not cause a loading effect for the small or medium output power.
21
The manufacturer part number is ATF51143, from Avago Inc. This is enchanment mode pHEMT device, designed with 6400 μm
gate-width and with 46 gate fingers. The packaged device information is given in [86].
22
The manufacturer part number is ATF51143, from Avago Inc This is enchanment mode pHEMT device, designed with 800 μm
gate-width and with 16 gate fingers. The packaged device information is given in [87].
36
Ropt,i(ω)
Ropt,i(ω)
Li
i1
Xopt(ω)
i2
Ropt,i(ω)
Li
Xopt(ω)
i3
Li
Xopt(ω)
ZL
Figure 3.25: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω .
Note that dummy termination is neglected to push all current to the load RL. i denotes 1, 2..n
•
Layout design
PCB selection i.e. thickness h and dielectric constant εr are important. For an instance, having a standard
routing to connect two lumped elements size of 3060, with the allowable minimum width of 30 mils. In this
case of the PCB which has thicker h, has the advantage to minimize line inductance, assuming εr is
identical. However, as a trade-off stray capacitance increases, although via hole inductance is reduced.
As a guideline, it is strongly recommended to use h of 0.762 mm and εr of 3.66 (Rogers properties) to
design DA covering bandwidth up to 2 GHz.
As far as PCB is concerned, the self resonance frequency of the board as high as possible (as a rule of
thumb). It is not easy to measure the frequency but some details are given in [88]. For high current
handling and to keep the frequency higher as possible, one can investigate the coupling effects with the
23
aid of a full-wave simulator (e.g. CST , HFSS or others). Figure 3.26 shows via-hole full-wave simulation
to study optimum spacing for a selected diameter via hole [164]. The result revealed the spacing must be
at least 2 times of the diameter in order to reduce the coupling at higher frequencies (up to 4 GHz).
General layout guidelines e.g. component placements, RF and DC routing, general layout rules, etc will
be explained in Appendix A.
spacing, s
diameter, d2
diameter, d1
Figure 3.26: Differential via-hole study to understand coupling effect for optimum grounding
potential, especially at higher frequency.
•
Full-wave simulation/Layout Optimization
Typically, a PCB (Printed Circuit Board) design goes through many prototypes passes to solve
unintended coupling problems through measurements and modifications based on experience, often late
in the development cycle. Hence, it is highly desirable to have an accurate simulation tool that can predict
unwanted coupling in the layout without actually fabricating a PCB [89] – [90]. Design methodology with
full-wave Electromagnetic (EM) simulation is adopted in this work to minimize design cycle time and avoid
tedious optimization. Two prototype DA boards developed in Chapter 6 require minimum optimization in
23
3D EM simulator, Computer Simulation Technology, from Darmstadt, Germany. Details can be achieved at www.cst.com.
37
board level. Irrelevant and insignificant details such as curved transmission line bends, small holes or
gaps could cause long period of simulation time due to the fine meshing requirements. Fine mesh
produces more accurate results, but suffers from longer computational time due to high density of
meshing, whereas coarse mesh requires less computational time, but may compromise the accuracy.
Therefore, there is always a tradeoff between computational time and accuracy. Radiation boundaries are
used in order to terminate the field so there is no electromagnetic energy reflected back to the object that
is being simulated. The minimum distance to the radiation boundary is quarter-wavelength (λ/4) at the
lowest frequency of interest. In CST there are several types of solvers. The time domain solver is a
powerful algorithm that is able to perform a simulation for a broad frequency range. The frequency
domain solver is able to solve an electromagnetic problem at a single frequency at a time. The frequency
domain solver is suitable, as an example in Chapter 6, more than 90 excitation ports were required in the
simulation [21].
Modeling with full-wave EM simulator including PCB layers stack-up, via holes, indium foil, grounded
heat-sink, and RF connectors modeling [21] are considered. For GaN power transistor, grounded
24
heat-sink is attached at bottom layer via indium foil and multiple screws, is shown in Figure 3.27. The
25
boards has 4 bigger diameter (5 mm) screws mounted to hold the grounded chassis and 2 smaller
diameter (1.4 mm) screws to mount the GaN amplifier to the chassis. Bottom layer of the PCB has solder
resist, and, bigger area of indium foil is filled in between of the bottom layer and grounded heat-sink. The
model of the RF connector is developed in section 4.4.3. Note that active and passive device models will
not be placed during the EM simulation.
Screw diameter of
5mm & 1.4mm,
respectively
Multilayers
PCB
Indium
foil for
electrical
and
PA
Grounded heat-sink
Figure 3.27: Cross-sectional diagram of high power GaN amplifier and PCB.
26
27
The EM simulation design flow is begun with importing the ODB++ file from Cadence to CST
environment, defining port and boundary region, exporting the S-parameter to ADS simulator until
28
optimizing the layout in Harmonic Balance (HB) simulation before release the gerber file for the
fabrication. Each active and passive component is terminated with discrete lumped port in CST, and total
of 90 ports for the first DPA development (section 6.2) were created. Therefore, the layout information
(*.s90 file) is exported to ADS to evaluate complete power performance. All passive and active
components model are connected to the appropriate ports in ADS.
24
The indium foil is received from Indium Corporation, and thermal conductivity of the copper foil is 0.34W/cm at 85 °C. The foil part
number is IN52-48SN (0.004" thickness), Indium Corporation Inc., North Carolina, US
25
The screw thread is designed in a way to provide good grounding with heat-sink.
26
ODB++ file is a PCB gerber file, and it was created to bring some order to the transfer of board date to manufacturer.
27
Cadence Design System, from San Jose, US, and further details can be learned at www.cadence.com.
28
ADS Co-Simulation assisted with CST is performed in ADS environment. This simulation allows the optimization the geometry of
the layout, and while performing complete optimization in the HB simulation (assisted CST).
38
3.5 Conclusion
The distributed amplification concept and theoretical analysis of the DA are presented with several
approaches i.e. Beyer, Niclas and McKay model). The Beyer’s method based on the two-port theory
considers only unilateral small signal transistor model (i.e. Cgd = 0). The Niclas’s method is more general
because there is no simplifying assumption regarding the transistor model, using Y matrix where total
voltages and currents are related. Finally, McKay’s method uses the normalized transmission matrix
approach has the advantage of clearly displaying the traveling wave nature of the DA, even the input and
output lines are constructed with lumped elements. Nevertheless, Beyer’s method still favorable choice to
synthesize DA input/output network to form an estimation gain-bandwidth response in many DA works.
Design methodology of practical DA is presented in the end of the chapter, which provides guidelines to
the designers to realize a DA in an effective time, and without any tedious optimization in board level. It is
necessary to identify effective input and output impedance of the packaged device to synthesize the gate
and drain line networks by means of image impedance characteristics. Layout design guidelines from
PCB selection, full-wave simulation, layout optimization, via-hole simulation, etc should be taken into
consideration during the design stage.
39
Chapter 4.
Efficiency Analysis in Distributed Amplifiers
Distributed amplifiers (DAs) are known for their flat gain, linear phase, and low return losses over wide
bandwidth [28]. They represent attractive candidates for Software Defined Radio (SDR) applications [11],
[91]. One of the major challenges in designing DA is to achieve high efficiency [5], [92]. Several
researchers have addressed the problems of low efficiency and output power of DAs, and suggested
solutions to overcome these limitations [83], [93] – [108]. To increase efficiency of the DA, drain current
from each transistor must be pushed to the load termination while mitigating the effect of the drain
termination [11], [98], and this is known as non-uniform drain line or impedance tapering, where
cancellation of backward current waves at each junction for characteristic impedance equal to Zo/n, where
Zo is the characteristic impedance of the first section and n is the number of section [98], [107]. Work by
[108] showed DA without an output synthesis transmission line, and delay equalization is instead
provided by impedance matched line sections between common-source (CS) and common-gate (CG)
devices. Non uniform DA design methodology as function of optimum power load of each device to
maximize power and efficiency demonstrated by [102] - [103].
This chapter discusses on virtual impedance analysis due to multi-current sources and technique to
increase efficiency. High efficiency DA development demonstrated output power of ~27 dBm, gain of 8 dB
and PAE >30% covering 10-1800 MHz [13], [83]. Furthermore, dual fed DA with termination adjustment is
introduced to improve power-efficiency response over conventional DA, and the prototype board
demonstrated output power of ~28 dBm, gain of 10 dB and PAE >20% [23]. The amplifier demonstrated
best in power-efficiency performance within range 100-800 MHz with low DC supply voltage [23].
4.1 Efficiency Limitations in DA
Efficiency of conventional DA has never demonstrated PAE of more than 20% [5], [7]. This is primarily
due to the current splitting on the drain line into two branches forming waves traveling towards the output
load termination, and waves traveling towards the dummy termination. Each device transistor injects a
current of gmvgs into each of drain of the transistor, where gm and vgs are trans-conductance and gate
source voltage, respectively. Since the drain of each transistor sees an impedance of Zπ in both
directions, hence half of this current travels to the left and half to the right, and this is illustrated in
Figure 4.1. The drain impedance seen in each direction Zπ is given as
Ld (1 −
Zπ =
f 2 −1
)
2
fc
(4.1)
4C d
where Ld and Cd are inductive and capacitance elements to form artificial transmission line along the drain
line, respectively. fc is known as cut-off frequency of the transmission line.
Current flowing to the load termination, IdR and dummy termination, IdL can be deduced from network
shown in Figure 4.1. Each low pass network, Ld -Cd is contributing image propagation factor, θd along the
drain line. Applying superposition theorem [109] to the network shown in Figure 4.1, the current towards
drain termination, IdR can be derived as the following
40
Id =
R
− ( n −3 / 2 )θ d
− ( n −5 / 2 )θ d
− ( n −( n + 2 ) / 2 )θ d
1 ⎡ − ( n−1/ 2)θd
⎤ 1 −θ2 n
I1e
+ I 2e
+ I 3e
+ ......I n e
I K e −θ
⎥⎦ = 2 e ∑
2 ⎢⎣
K =1
d
d ( n− K )
,
(4.2)
where n is number of transistor sections. The network is assumed to be lossless. Similarly, applying
Superposition theorem [109], current towards dummy termination IdL is derived as the following
Id =
L
θ
− θd
− 2θ d
− ( n −1)θ d
1 ⎡ − (1 / 2 )θ d
⎤ = 1 e− 2
+ I 2 e + I 3e
+ ......I n e
I 1e
⎥⎦ 2
2 ⎢⎣
d
IdL Ld/2
ZOTL
Zπ
Zπ
i1
Cd/2
n
∑I
K =1
K
e −θ d ( K −1) .
(4.3)
IdR
Ld
Cd/2
i2
in
ZOTR
Figure 4.1: Impedance Zπ seen by each transistor in both directions, of half right and half left.
For the real resistive termination for load and dummy termination, the ratio of power absorption between
load termination and dummy termination is given by
Pratio
−
θd
n
2
2
1
R
I d ℜ{Z OT } e ∑ I K e
Pload
K =1
,
=
=2
=
2
2
θd n
1 L
L
Pdummy
−
I d ℜ{Z OT }
e 2 ∑ I K e −θ d ( K −1)
2
R 2
−θ d ( n − K )
(4.4)
K =1
where ZOTR and ZOTL are load termination and dummy drain termination, respectively. The notation ℜ is
referring to real part and in the following section, ℑ will be referring to imaginary part.
(4.4) shows power ratio between load termination and dummy termination is equal if the both termination
impedance have equal characteristics. It is clear that half fundamental RF energy is wasted in the dummy
termination from the overall fundamental RF energy generated by all the transistor sections. The following
section will lead into the technique to improve efficiency.
4.2 Virtual Impedance analysis due to multi current sources
DA will have impedance as a result of the injected signals at each device output node [11]. Figure 4.2 is a
simple schematic of two ideal current source combined at a common node connected to a load R. Each
current source has Thevenin driving impedance e.g. R1 and R2, is shown in Figure 4.2. However, for
simplicity, the Thevenin driving impedances R1 and R2 are neglected (as well as in the following analysis),
and with assumption that the loading effect for the medium power devices are not significant when loaded
into the drain line. Thus, the impedance seen by each current source due to injected sources can be
called as virtual impedance.
41
As shown in Figure 4.2, the current i(t) through the load would be sum of the two sources ii(t) and i2(t).The
complex current source and response may be represented simply by applying Euler’s identity [109]. The
i1(t) and i2(t) source thus becomes
i1 (t ) = I1e j ( wt +θ1 ) = I1 cos(wt + θ1 ) + jI1 sin(wt + θ1 ) ,
(4.5)
i2 (t ) = I 2 e j ( wt +θ 2 ) = I 2 cos( wt + θ 2 ) + jI 2 sin( wt + θ 2 ) ,
(4.6)
where I1 and I2 representing magnitude of the complex current source and θ1(t) and θ2(t) are independent
phase value, respectively.
The impedance Z1 looking into common node with i2(t) in parallel with R is what current source vector i1(t)
is loaded with. By simplifying Figure 4.2 and applying Thevenin theorem, it shown in Figure 4.3. Thus the
impedance Z1 can be derived as following
Z1 = v (t ) / i1 (t ) =
[i1 (t ) + i2 (t )] ,
R
i1 (t )
(4.7)
⎡ I e j ( w(t ) +θ 2 ) ⎤
= R ⎢1 + 2 j ( w(t ) +θ ) ⎥ = R ⎡1 + I 2 (cos(θ − θ ) + j sin(θ − θ ))⎤ .
2
1
2
1 ⎥
⎢
1
I 1e
⎣⎢
⎦⎥
⎣ I1
⎦
(4.8)
If there is no phase offset or in-phase combining (θ2 = θ1) is applied in DA, the amplitude of reactive term
becomes zero. Thus, the virtual impedance Z1 is positive real. Hence the impedance Z1 can be simplified
as below
⎡ I ⎤
Z 1 = R⎢1 + 2 ⎥ .
⎣ I1 ⎦
(4.9)
i1(t)
R2
R1
Z1
i2(t)
i(t)
R
Figure 4.2: Two current sources are combining at a single node.
42
i1(t)
+
Z1=v(t)/i1(t)
v(t)=[i1(t)+i2(t)]R
R
-
Figure 4.3: Simplification of circuit from Figure 4.2 to understand Z1.
From (4.8), the normalized virtual impedance real and imaginary part Z1/R vs. (θ2-θ1) for few cases of I2/I1
(from 0.1 to 2) is illustrated in Figure 4.4. For the lower ratio of I2/I1, e.g. 0.1, the real Z1/R is almost 1 and
increases to 3, when I2/I1 is 2. The imaginary Z1/R is remained unchanged for any ratio of I2/I1. This is an
evidence that current source properties i.e. magnitude and phase can be adjusted to achieve desire of
Z1/R.
Consider multi-current sources are combined at a common node connected to a load R, as shown in
Figure 4.5, virtual impedance seen by the current sources in two directions, which is upper and right
direction Zu(k) and Zr(k), respectively can be determined. Note that the Thevenin driving impedance of the
current sources are neglected for simplicity, and k = 1, 2, 3 .. n. RF excursion swing of voltage and
current of each source is depending on Zu(k), and Zr(k) will determine the impedance that shall be
synthesized along the drain artificial transmission line. Zu(1) is begin by finding Norton equivalent network
across port aa’, shown in Figure 4.5. Norton equivalent impedance, RN can be determined by removing all
current sources except the first one ( i2 = i3 ... = in = 0 ), thus RN = R. Norton equivalent current, iN across
port aa’ can be determined applying Superposition theorem. When finding iN, port aa’ must be shorted,
and i N = i2 + i3 + ... + in . Current generator, i1 and Norton equivalent network of Figure 4.5 can be
simplified to Figure 4.6. Thus, the virtual impedance Zu(1) seen by the current generator, ii (from
Figure 4.5) can be deduced to
Z u (1) =
v ⎡ (i1 + iN ) RN ⎤ ⎡ i2 + i3 + ... + in ⎤
=
⎥ = ⎢1 +
⎥R .
i1 ⎢⎣
i1
i1
⎦ ⎣
⎦
(4.10)
The ratio I2/I1 is varied from 0.1 to 2, and imaginary part not change with I2/I1.
By substituting ik
= I k e j ( wt +θ k ) , where k = 1, 2 .. n, one can derive the virtual impedance
⎡ I
⎤
I
Z u (1) = R ⎢1 + 2 (cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) ) + ... + n (cos(θ n − θ1 ) + j sin(θ n − θ1 ) )⎥ ,
I1
⎣ I1
⎦
(4.11)
where I1, I2 .. In representing magnitude of the complex current source and θ1, θ1 .. θn are independent
phase value, respectively.
43
2
1
0.5
ℑ{ Z1/R}
ℜ{Z1/R}
1.5
0.1
(θ2-θ1), rad/s
(θ2-θ1), rad/s
Figure 4.4: The plot of real and imaginary Z1/R vs. (θ2-θ1) for few cases I2/I1 from (4.8).
In similar manner, Zu(n-1) and Zu(n) seen by in-1 and in can be determined as
⎡
⎤
I
I
Z u ( n−1) = R ⎢1 + 1 (cos(θ1 − θ n−1 ) + j sin(θ1 − θ n−1 ) ) + ... + n (cos(θ n − θ n−1 ) + j sin(θ n − θ n−1 ) )⎥ ,
I n−1
⎣ I n−1
⎦
(4.12)
and
⎤
⎡ I
I
Z u ( n ) = R ⎢1 + 1 (cos(θ1 − θ n ) + j sin(θ1 − θ n ) ) + ... + n−1 (cos(θ n−1 − θ n ) + j sin(θ n−1 − θ n ) )⎥ .
In
⎦
⎣ In
(4.13)
Zr(1)
Zr(2)
Zr(n)
a
a'
Zu(1)
Zu(2)
Zu(n)
i1
i2
in
+
R
v
-
Figure 4.5: The virtual impedance, Zi seen by the current generator in two directions (Zu(k) and Zr(k)),
respectively and k = 1, 2, 3 .. n.
44
Zu(1)
a
+
iN
i1
vN
RN
a'
-
Figure 4.6: Simplification network of current generator, i1 and Norton equivalent network of Figure
4.5 to determine Zu(1).
It is clear from Figure 4.5, that Zr(1) = Zu(1) and Zr(n) = R, but, however Zr(n-1) is given as
Z r ( n −1) =
⎡ (i + i ) R ⎤ ⎡ i + i + ... + in ⎤
v
R,
=⎢ 1 N N⎥=⎢2 3
i1 + ... + in −1 ⎣ i1 + ... + in −1 ⎦ ⎣ i1 + ... + in −1 ⎥⎦
(4.14)
and substituting ik = I k e j ( wt +θ k ) into (4.14), then it can be deduced as
Z r ( n −1)
In
I2
⎡
⎤
⎢ 1 + I (cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) ) + ......... + I (cos(θ n − θ1 ) + j sin(θ n − θ1 ) ) ⎥
1
1
⎥.
= R⎢
⎢1 + I 2 (cos(θ − θ ) + j sin(θ − θ ) ) + ......... + I n −1 (cos(θ − θ ) + j sin(θ − θ ) ) ⎥
2
1
2
1
n −1
1
n −1
1
⎢⎣
⎥⎦
I1
I1
(4.15)
Zr(k) and Zu(k) as derived above must be satisfied to combine n section current sources to a single load R,
and assuming minimum loading effect of the output transistor. Beyer et al. have showed that gain in
conventional DA cannot be increased indefinitely by adding more sections losses associated with active
transistor resistances [4], [110]. Typically, n = 4 is applied in DA [83].
From (4.11) – (4.15), for k = 1, 2 .. 4, the following set of equations are deduced
Z u (1) / R = 1 +
+
I4
(cos(θ 4 − θ1 ) + j sin(θ 4 − θ1 ) ) ,
I1
Z u ( 2) / R = 1 +
+
I2
(cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) ) + I 3 (cos(θ3 − θ1 ) + j sin(θ3 − θ1 ))
I1
I1
(4.16)
I1
(cos(θ1 − θ 2 ) + j sin(θ1 − θ 2 ) ) + I 3 (cos(θ3 − θ 2 ) + j sin(θ3 − θ 2 ) )
I2
I2
I4
(cos(θ 4 − θ 2 ) + j sin(θ 4 − θ 2 ) ) ,
I2
(417)
45
Z u ( 3) / R = 1 +
+
I4
(cos(θ 4 − θ3 ) + j sin(θ 4 − θ3 )) ,
I3
Z u ( 4) / R = 1 +
+
I1
(cos(θ1 − θ3 ) + j sin(θ1 − θ3 ) ) + I 2 (cos(θ 2 − θ3 ) + j sin(θ 2 − θ3 ) )
I3
I3
(4.18)
I1
(cos(θ1 − θ 4 ) + j sin(θ1 − θ 4 ) ) + I 2 (cos(θ 2 − θ 4 ) + j sin(θ2 − θ4 ))
I4
I4
I3
(cos(θ3 − θ 4 ) + j sin(θ3 − θ 4 )) ,
I4
(4.19)
Z r (1) / R = Z u (1) / R ,
(4.20)
I3
(cos(θ3 − θ1 ) + j sin(θ3 − θ1 )) + I 4 (cos(θ 4 − θ1 ) + j sin(θ 4 − θ1 ))
I1
I1
,
Z r ( 2) / R = 1 +
I2
1 + (cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) )
I1
I4
(cos(θ 4 − θ1 ) + j sin(θ 4 − θ1 ))
I1
,
Z r ( 3) / R = 1 +
I3
I2
1 + (cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) ) + (cos(θ 3 − θ1 ) + j sin(θ 3 − θ1 ) )
I1
I1
Z r ( 4) / R = 1 .
(4.21)
(4.22)
(4.23)
Results of normalized real and imaginary Zu(k)/R, (k = 1, 2, 3 and 4) vs. (θa - θb), are illustrated in Figure
4.7. (θa - θb) 29 is referring to phase difference, and a and b are referring to any case as given in
(4.16) - (4.19). The real and imaginary part Zu(k)/R and Zr(k)/R are plotted for same magnitude of current
sources, where I1 = I2 = I3 = I4. From Figure 4.7, for in-phase combining (θa - θb) = 0, then the real part
Zu(k)/R = 4 and imaginary part Zu(k)/R = 0. As (θa - θb) = π/2 rad/s, the real part vanishes to 0 and imaginary
part has highest reactance. The plot of Zr(k)/R, (k = 1, 2, 3 and 4) vs. (θa - θb), where I1 = I2 = I3 = I4 is
shown in Figure 4.8. The real part Zr(k)/R value is reduces and imaginary part is null for in-phase
combining (θa - θb) = 0. Real and imaginary part Zr(2)/R, Zr(3)/R and Zr(4)/R are almost constant for
(θa - θb) ≤ π/2 rad/s. As (θa - θb) increases, the real part vanishes.
29
(θa - θb) is the different phase between two current sources properties, as an example, Zu(1)/R, θa - θb =θ2 - θ1 = θ3 - θ1 = θ4 - θ1 .
And the different phase can be determined from (4.16) – (4.19).
46
Zu(k)/R
ℑ{Zu(k)}
ℜ{Zu(k)}
(θa - θb) rad/s
Figure 4.7: Real and imaginary Zu(k)/R (k = 1,2, 3 and 4) vs. (θa - θb) for identical current sources,
I1 = I2 = I3 = I4. The response Zu(1)/R = Zu(2)/R = Zu(3)/R = Zu(4)/R.
k=1
ℑ{Zr(k)/R}
ℜ{Zr(k)/R}
k=2
k=3
k=4
k=1
k=2
k=3
(θa - θb) rad/s
(θa - θb) rad/s
Figure 4.8: Real and imaginary Zr(k)/R (k = 1, 2, 3 and 4) vs. (θa - θb) for identical current sources,
I1 = I2 = I3 = I4. For k=4, the imaginary part is null.
Important point to be noticed that to match to standard R of 50 Ω, Zu(k) equals to 200 Ω (k = 1, 2, 3 and 4).
However, to achieve Zu(k) < 200 Ω (power matching), R has to be lower than 50 Ω, and therefore an
impedance transformation from R to 50 Ω is needed. To avoid impedance transformation, one possibility
is to achieve Zu(k) < 200 Ω while remaining R = 50 Ω, the current sources properties e.g. I1, I2 .. In and θ1,
θ2 .. θn can be adjusted. Table 4.1 shows tabulated results of Zu(k)/R and Zr(k)/R (k = 1, 2, 3 and 4) for
various magnitude and phase selection. From (4.16 – 4.23), the real part of Zu(k)/R and Zr(k)/R are given in
the Table 4.1, and imaginary part is not shown, but, however, will be absorbed in the input and output
transmission lines. For same magnitude and in-phase combining current source, ℜ{Zu(k)/R}are equal, and
ℜ{Zr(k)/R}is reducing from 4, 2 and to 1, for all k. Figure 4.9 shows Zr(k)/R seen by each current source and
evaluated according to (4.20) – (4.23). Either adjustment of magnitude or phase of the current source, will
result in ℜ{Zu(k)/R} reduction.
As an example from Table 4.1, for in-phase combining, and when final current magnitude is reduced by
factor 10, then ℜ{Zu(1)/R} = ℜ{Zu(2)/R} = ℜ{Zu(3)/R} = 3.1, but ℜ{Zu(4)/R} = 31. Therefore, the forth (or last)
section can be placed with high-fτ transistor (having lower device periphery) which may not contribute
power to the load and absorb power at certain frequency, but simply acts as an active load matching. In
similar manner, lower ℜ{Zu(k)/R} can be achieved for case of magnitude fixed while adjusting the phase.
47
With adjustment of both properties i.e. magnitude and phase of the current sources, ℜ{Zu(k)/R} can be
reduced to lower value. As shown in Table 4.1, when I1 = 1, I2 = 0.7, I2 = 0.4 and I2 = 0.1, and θ1 = 0,
θ2 = π/6, θ2 = π/4 and θ2 = π/2, the value of ℜ{Zu(1)/R} = 2.1, ℜ{Zu(2)/R} = 3.2, ℜ{Zu(3)/R} = 3.67 and
ℜ{Zu(4)/R} = 20. To achieve this, the device periphery of the transistors can be tapered [113] while
adjusting the gate line characteristics to provide phase condition. Therefore, it is choice of designer to
adjust the Ik andθk to obtain reasonable Zu(k)/R and Zr(k)/R.
I1
1
1
1
1
1
1
1
1
1
1
I2
1
1
1
0.7
1
1
1
1
1
0.7
I3
1
1
0.7
0.4
1
1
1
1
0.6
0.4
I4
1
0.1
0.1
0.1
1
1
1
0.1
0.1
0.1
θ1
0
0
0
0
0
0
0
0
0
0
θ2
0
0
0
0
0
0
π/6
0
0
π/6
θ3
0
0
0
0
0
π/5
π/4
0
π/5
π/4
θ4
0
0
0
0
π/4
π/4
π/2
π/4
π/4
π/2
ℜ{Ζu(1)/R}
4
3.1
2.8
2.2
3.7
3.5
3.38
3.07
2.55
2.16
ℜ{Ζu(2)/R}
4
3.1
2.8
3.14
3.7
3.5
3.82
3.07
2.55
3.22
ℜ{Ζu(3)/R}
4
3.1
4
5.5
3.7
3.6
3.79
3.07
3.86
3.67
ℜ{Ζu(4)/R}
4
31
28
22
3.1
3.4
3.66
22.2
21.06
20.75
ℜ{Ζr(1)/R}
4
3.1
2.8
2.2
3.7
3.5
3.38
3.07
2.25
2.16
ℜ{Ζr(2)/R}
2
1.55
1.4
2.9
1.85
1.75
1.93
1.53
1.27
1.38
ℜ{Ζr(3)/R}
1.33
1.03
1.03
1.04
1.23
1.29
1.39
1.02
1.03
1.04
ℜ{Ζr(4)/R}
1
1
1
1
1
1
1
1
1
1
Table 4.1: Zu(k)/R and Zu(k)/R for various Ik and θk selection (k = 1, 2, 3 and 4).
It is clear that to combine the current from each source at single node (at the load R), the virtual
impedance seen by the current sources in two directions (Zu(k) and Zr(k)) must be presented to each
current source. If current source sees high Zu(k) (e.g. 200 Ω), it is not possible to deliver power from each
current source due to RF current swing limitation. Certainly, it is possible to achieve Zu(k) < 200 Ω while
remaining R = 50 Ω, as long as the equations (4.16) – (4.23) are satisfied. In (4.1), the impedance seen
by each current source loaded with constant-k ladder network transmission line, typically 50 Ω
impedance, limits the excursion of RF current swing. Nevertheless, to maximize the current swing it is
necessary to match to the optimum power load of each current source (or transistor) [111], and in DA
reducing Zu(k) will increase power from each source. But, however, it is important to note that there is
boundary limitations in practical realizations to achieve lower Zu(k) while remaining R = 50 Ω, such as
device periphery ratio of the transistor, gate line controlling, etc.
For unequal magnitude of the current source can be achieved with capacitively coupled technique [35].
The unequal injection of current source is due to different of vgs drop along the gate line is illustrated in
Figure 4.10. An external capacitor is coupled in series between the lumped inductance and input parasitic
device capacitance Cgs, and the external capacitor controlling the voltage drop across the Cgs. Thus by
varying the voltage drop ratio along the gate line, it is possible to tailor the input excitation to individual
transistors. From Figure 4.10, when ωCgsRgs ≤ 1, the equivalent capacitance loading the gate line is
48
Cg =
C a C gs
C a + C gs
,
(4.24)
where Rgs is series gate resistance of the active device. Rgs is not shown in Figure 4.10 for simplicity.
Voltage drop across the Cgs junction can be deduced as
vgs =
Ca
Vi ,
Ca + C gs
(4.25)
where Vi is voltage that appears as shown in Figure 4.10. For lossless or ideal gate line, Vi magnitude is
approximately same for any nodal stage. Each device transistor injects a current of gmvgs into each of
drain of the transistor. Notation gm and vgs are referred to trans-conductance and gate source voltage of
the transistor, respectively.
Zr(n)
Zr(2)
Zr(1)
i1
i2
in
R
Figure 4.9: Zr(k) is evaluated according to (4.20) – (4.23), to design artificial transmission. The
output capacitance parallel to the current source typically known Cds will be absorbed in the
artificial transmission line design.
vgs1
Cgs
vgs2
-
Cgs
+
+
Ca
Cgs
vgsk
+
Ca
Ca
Pin
Lg/2
V1
Lg
V2
Lg
Vk
Lg/2
Rgt
Figure 4.10: Input gate line coupled with external capacitor in series with Cgs. Note that the
elements may have different values if unequal injection is required.
49
However, the phase adjustment of the current source is difficult to realize and keep in mind that the
constant-k ladder network behavior changes with respect to frequency. Stengel et al. invented a
technique to drive the gate line with a drive generator circuit to produce modulation of virtual load
impedance at each amplifier stage [112] and new DA architecture to provide programmable constructive
vector signal combining at a fundamental frequency along with programmable destructive at harmonic
30
frequencies [114]. A simple approach as shown in [83], phase adjustment is achieved with non-uniform
gate line design where gate line impedance is adaptively reduced to provide better phase
synchronization.
4.3 High Efficiency DA Development
4.3.1
Simulation Analysis
Validation of the concept above for equal magnitude and in-phase combining where I1 = I2 = I3 = I4 = 1)
and (θ1 = θ2 = θ3 = θ4 = 0) have been selected (from Table 4.1), as R = 50 Ω selection leads to
ℜ{Zu(1)} = ℜ{Zu(2)} = ℜ{Zu(3)} = ℜ{Zu(4)} = 200 Ω, and ℜ{Zr(1)} = 200 Ω, ℜ{Zr(2)} = 100 Ω, ℜ{Zr(3)} = 67 Ω, and
ℜ{Zr(4)} = 50 Ω, and imaginary part not exists. This is illustrated in Figure 4.11. For simplicity, a
hypothetical drain terminal of a transistor has been modeled as an ideal current source with parallel
resistance (high impedance, e.g. 1M Ω) [83]. To additively combine the currents at each junction (as in
Figure 4.11), phase synchronization between the current source and the transmission line is crucial.
Since delays of transmission lines θd(k) vary linearly with frequency, making the current source delays also
vary with frequency would guarantee delay matching between the sources and the transmission lines.
Putting current source delays as θ1 = 0o, θ2 = -1*10o*1 GHz/freq, θ3 = 2*10o*1 GHz/freq and
31
θ4 = -3*10o*1 GHz/freq, respectively. The notation freq is referring to frequency in AC simulation (ADS )
and θd(k) is simply set to a fixed real value e.g. 40°. Figure 4.12 shows vector diagram of magnitude and
phase of the current properties for the Figure 4.11. At every junction, the resultant magnitude of the
sources (ib, id and if) are constructive for in-phase combining between ia and i2, ic and i3 and ie and i4.
Power delivered by each current source is shown in Figure 4.13. It indicates that calculated power of
100 W is achieved across the frequency, where all the sources are presented with exactly the required
hypothetical optimum impedance of 200+j*0Ω at all frequency. Phase coherency between the current
sources and the phase of the transmission must be well matched to achieve maximum power delivery
from the sources to the output line over the entire frequency range. Analogous results are obtained for
various case of Ik and θk selection (k = 1, 2, 3 and 4) from Table 4.1.
θd1
ia
θd2
ib
-
Zr(1)
Zu(2)
j(wt+θ )
i1 =I1e
1
θd3
id
+
v2
-
Zr(2)
Zu(3)
i2 = I2ej(wt+θ2)
ie
θd4
if
Zr(3)
Zr(2)
Zr(1)
Zu(1) +
v1
ic
+
Zr(3)
v3
-
i3 = I3ej(wt+θ3)
iL
Zr(4)
Zu(4)
+
v4
-
Zr(4)
i4 = I4ej(wt+θ4)
+
R vL
-
Figure 4.11: Circuit showing multi-current sources to combine at a single load termination,
R =50 Ω.
30
Stengel et al. showed in [114], that harmonic components of the current sources can be controlled with I/Q baseband signal
injection to the gate line.
31
Advanced Design System 2009, from Agilent Inc., San Jose, CA, and it is an electronic design automation software system.
50
However, in reality, lumped inductance with parasitic capacitance (of the transistor) will form a constant-k
artificial transmission line along the drain line which is found suitable for low microwave region
[115] - [116]. Again, a similar analysis is performed to understand the power delivery behavior in the
presence of lumped inductance and capacitance. Figure 4.14 shows circuit representation of ideal current
source with lumped inductance and capacitance. Cut-off frequency ωc is set to 2.12 GHz. Transmission
line has non-uniform impedance, Zr(1) = 200 Ω, Zr(2) = 100 Ω, Zr(3) = 67 Ω, and Zr(4) = 50 Ω, and imaginary
part not exists. Careful phase consideration of each current source must be taken into account due to the
delay of each L-C combination with respect to the frequency. Therefore, delay or phase velocity equation
of the constant-k artificial transmission line is defined for the current source delay θd(k) as given by
⎡
θ d ( k ) = cos −1 ⎢1 −
⎣
2ω 2 ⎤
⎥.
ωc 2 ⎦
(4.26)
θd4
i4
θd1
i1
ia, i2
θd3 θd2
i3
ib
ic
iL
ie
id
if
Figure 4.12: Vector diagram of magnitude and phase of the current properties for the Figure 4.11,
where magnitude and phase of the current sources are equal. i1 is set to be reference.
Figure 4.13: Power delivered by each current source with matched delay values connected to the
output transmission line. Note all the sources deliver maximum power and have the same energy
level over the frequency range.
51
The θ1 = 0o, θ2 = -1*θd(1), θ3=-2*θd(2) and θ4=-3*θd(4), respectively. Figure 4.15 shows power response of
the current sources across wide frequency range. At low frequency (close to DC), maximum power
delivers by each current source. The power response is degrading as frequency increases towards ωc.
Due to the fact that phase delay changes with frequency, it is difficult to achieve phase coherency for
optimum current combining at each junction (as in Figure 4.11). The further the current source located
(closer to the load termination R), power degraded earlier with respect to frequency, and certain
frequency it absorb power from the line (as sees negative impedance). Need to keep in mind that power
delivered by each transistor follows the real part impedance. Note that a strong peaking occurred as
signal closer to ωc, especially at the first and last section. In the following section, a technique to
compensate phase delay by designing non-uniform gate line to improve power delivery from each
transistor will be discussed [83].
Zr(3)=67Ω
Zr(2)=100Ω
Zr(1)=200Ω
30 nH
0.75 pF
15 nH
Zr(3)=50Ω
10 nH
2.25 pF
1.5 pF
7.5 nH
3 pF
50 Ω
Figure 4.14: Circuit shows an analysis of drain line tapered with constant-k terminated with 50 Ω
load termination. All the current sources loaded with parallel resistor of 1 MΩ.
Figure 4.15: Power delivered by each ideal current source non-uniform drain line with lumped
elements. Note the graph colors (red is 1st source, blue is 2nd source, yellow is 3rd source and
green is 4th source, respectively).
4.3.2
Design Example of High Efficiency DA
As discussed in section 3.3, the design methodology i.e. from device selection, synthesizing gate/drain
line elements from device packaged values, until full-wave simulation/layout optimizations are applied in
this section. The basic design goal of the work is to achieve high efficiency for SDR driver PA
applications, and the power operation is ~27 dBm. Therefore, medium power device i.e. pHEMT device
52
32
(ATF511P8) is suitable. The low DC supply operation is required forr the device, which typically is about
4.5 V. Break-down voltage Vbk of the device is ~16 V, which is slightly lower than computation value from
(3.47). The drain loading effect of the device is not significant, but, however Xopt(ω) is important since it
determines the drain line cut-off frequency ωc. Copt of 4 pF is extracted by means of device modeling (with
inclusion of package properties). Therefore, effective drain line elements i.e. Li are synthesized according
to (3.48), to form desired ωc (~1.9 GHz). Dummy drain termination is eliminated to improve the efficiency
performance [83].
Simplified design schematic of 4-section pHEMT DA applying non-uniform drain line is shown in
Figure 4.16. m-derived section is implemented at both termination of gate line. Each device is fed with 5 V
drain supply voltage. Bias voltage of 0.44 V is applied to each gate resulting in class AB operation, with
quiescent current Idq of ~90 mA (~10% of Idss). A series gate resistor Rg(k) of 5 Ω is used at each section
for stability purpose. Power performance due to load termination R for n = 4 is investigated. The virtual
impedance seen by the transistor in both directions depending on selection as illustrated in section 4.2,
and can be computed as given (4.16) - (4.23). Thus, computation of the virtual impedance must be
repeated for different case of load termination, R. All the passive elements are slightly tuned in the
simulation level for optimum results, and the summary elements are tabulated in Table 4.2 33 . The gate
line impedance network remains unchanged for the analysis. The supply voltage and gate bias voltage is
fixed as previous value.
Ld2
Ld1
Cd1
Cga1
Lm1
Lg1
Lg2
R
Cga4
Cga3
Lg3
Cd4
Rg4
Rg3
Cga2
Ld4
Cd3
Cd2
Rg2
Rg1
Ld3
Lg4
Lg5
Lm2
Rgt
Cm2
Cm1
Figure 4.16: Simplified 4-section DA applying non-uniform drain line impedance. m-derived
section is implemented close to termination of gate line.
Simulated results input return loss S11 and output return loss S22, and power performance (PAE and gain)
for various load termination R are shown in Figure 4.17 and Figure 4.18, respectively. It is shown from
Figure 4.17 that the output return loss (S22) is dependent of R. Right selection of load termination, R is
important for optimum matching and power performance across wide frequency range. For example, R
within range of 8 Ω and 12.5 Ω are the optimum case. For best efficiency result (PAE >40%) across the
frequency range, R of 12.5 Ω is the optimum case. Constant-k non-uniform drain line network with lower
R (e.g. 5 Ω) is not effective. For the gate line termination Rgt is 50 Ω, optimum R is within range of 8 Ω to
12.5 Ω for case n of 4. For case R of 50 Ω, the power performance is degraded beyond 1400 MHz. This
analysis indicated that R is important to provide better phase equalization between gate and drain line.
The phase velocities synchronization between gate and drain line is achieved with non-uniform gate line
design as well [83]. A simple adjustment of Cga(k) and Lg(k) (for k = 4, as shown in Figure 4.10) offers
32
33
The detail of ATF511P8 device is given in [86].
Cd(k) (as given in Table 4.2) is referring to external capacitance to form desired ωc with combination of Copt.
53
power and efficiency improvement. The gate line impedance and dummy termination Rgt is adaptively
reduced in simulation level. When R of 50 Ω and Rgt of 41 Ω are selected, magnitude current of load
termination is improved by ~15 mA in simulation level compared with uniform gate line impedance across
frequency range. Figure 4.19 shows current of load termination comparison for case of with and without
non-uniform gate line impedance. In similar manner, for R of 12.5 Ω, the gate line impedance and dummy
termination are optimized in simulation level. It is important to note that the gate line properties are
dependent of termination R value. Detailed analysis of non-uniform gate line network for phase
synchronization with non-uniform drain line is not presented but it is recommended for future work.
Elements
R =5 Ω
R =8 Ω
R =12.5 Ω
R =25 Ω
R = 50 Ω
Ld1
3 nH
4.8 nH
7.5 nH
15 nH
30 nH
Ld2
1.5 nH
2.4 nH
3.75 nH
7.5 nH
15 nH
Ld3
1 nH
1.6 nH
2.5 nH
5 nH
10 nH
Ld4
0.75 nH
1.2 nH
1.88 nH
3.75 nH
7.5 nH
Cd1
6.6 pF
3.8 pF
2.1 pF
0.6 pF
n/a
Cd2
14.1 pF
8.48 pF
5.1 pF
2.1 pF
0.6 pF
Cd3
21.6 pF
13.2 pF
8.1 pF
3.6 pF
1.35 pF
Cd4
29.1 pF
17.9 pF
11.1 pF
5.1 pF
2.1 pF
Table 4.2: Summary drain line network elements for various load termination, R. n section is 4.
Cd(k) is the external shunt capacitance placed parallel to the transistor.
Figure 4.17: Simulated analysis of S11 and S22 for various load terminations, R for circuit shown in
Figure 4.16. The color: green is for R of 5 Ω, brown curve is 8 Ω, blue curve is 12.5 Ω, red curve is
25 Ω and orange curve is 50 Ω.
R of 12.5 Ω would be optimum selection due to good power performance and lower transformation
impedance ratio to 50 Ω compared with R of 8 Ω. Wideband impedance transformer design to match from
impedance of 12.5 Ω to 50 Ω will be discussed in the following section. High efficiency DA having
non-uniform drain and gate line networks terminated with R of 12.5 Ω and 50 Ω, respectively are chosen
54
to proof the concept in measurement level (will be discussed in section 4.3.4). Wideband impedance
34
transformer ratio 1:4 based on asymmetric parallel coupled line [117] - [118] is used in this design to
achieve impedance transformation from 12.5 Ω to 50 Ω covering frequency range of 10 - 1800 MHz, and
detail design of the transformer will be covered in the following section.
Figure 4.18: Simulated analysis of PAE and gain for various load terminations R for circuit shown
in Figure 4.16. The color: green is for R of 5 Ω, brown curve is 8 Ω, blue curve is 12.5 Ω, red curve
is 25 Ω and orange curve is 50 Ω.
Figure 4.19: Magnitude of load current for of non-uniform (red curve) and uniform (blue curve)
gate line design across the frequency range (10 – 1800 MHz).
34
Asymmetric coupled line demonstrated state-of-art performance in [118]. Due to quarter-wave transmission line, it consumes
huge size area. Therefore, the intention of the transformer design is to meet the requirements of impedance transformation over the
wide frequency with minimum insertion loss, to proof the high efficiency DA concept.
55
4.3.3
Broadband Impedance Transformer Design
Recent works by [120] – [124], demonstrated impedance transformer for microwave applications.
Coupled transmission lines have been suggested as a matching element due to greater flexibility and
compactness in comparison to quarter-wave transmission lines [121] – [122]. The quarter-wave
transformer is simple and easy to use, but it has no flexibility beyond the ability to provide a perfect match
at the center frequency for a real valued load. The coupled line section provides a number of variables
which can be utilized for matching purposes and these variables are the even and odd mode impedances
and loading of the through and coupled ports [118]. Recent work by [118] demonstrated fractional
bandwidth of more than 100% at -20 dB reflection with asymmetric coupled lines implementation in
nonhomogenous medium. A microstrip is one of the most commonly used classes of transmission lines in
nonhomogenous medium. Figure 4.22 shows general coupled line configuration, and coupled and
through ports can be loaded with an external impedance termination to extend bandwidth [118].
Figure 4.20 can be represented in two-port network, as in Figure 4.21.
The magnitude of the reflection coefficient at port 2 [119] is equal to
⎛ Z ( Z , Z ' 'ij , Z L − Z g
S 22 dB = 20 log⎜ IN ij
⎜ Z IN ( Z ij , Z ' 'ij , Z L + Z g
⎝
⎞
⎟,
⎟
⎠
(4.27)
where ZIN is the input impedance of the transformer, which is a function of the load ZL, impedance matrix
elements of coupled lines Zij, and arbitrary load Z’’ij (i and j are the indexes of the matrix elements).
Design equations of the asymmetric coupled in nonhomogenous medium can be obtained from [115].
When loaded the coupled and through ports with stepped impedance transmission line the operating
bandwidth of the transformer has increased by three times in comparison to the traditional quarter-wave
transformer [118]. However, in this work, bandwidth is further increased by creating an impedance
transformer using more coupled line sections connected in series [21], [117]. It consists of two coupled
transmission line sections, as illustrated in Figure 4.21. Each section is quarter-wavelength long at the
center frequency of operation. The impedance transformation of 12.5 Ω to 50 Ω is achieved between two
diagonal ports of the section. The remaining ports are interconnected by a stepped impedance
transmission line. This interconnection widens the operating frequency band and compensates for the
differences in electrical lengths of the coupled lines for the c and π modes [125] in nonhomogeneous
medium (assuming microstrip realization).
Figure 4.20: General coupled line configuration. The four-port section is reduced to a two-port
with coupled and through ports can be loaded with an external impedance termination [118]. In
this figure, through port is terminated with termination impedance Z4.
56
Figure 4.21: Two-port network representation for the coupled line transformer [118].
Coupled lines
Vout
Vin
Z03, l3, γ3 Z04, l4, γ4
1’’
Z01, l1, γ1
2’’
Z02, l2, γ2
Stepped impedance sections
Figure 4.22: Proposal circuit of the compact impedance transformer, and the impedance
transformation from 12.5 Ω to 50 Ω.
From Figure 4.22, an analysis of series stepped impedance of port 1″2″ is carried out based on [118],
thus, the impedance matrix elements are found to be
( Z12(1) ) 2
Z 012
Z = Z − ( 2)
=
,
Z
coth(
γ
l
)
−
01
11
Z11 + Z11(1)
( Z 01 coth(γ 1l1 ) + Z 02 coth(γ 2l2 )) ⋅ sinh 2 (γ 1l1 )
"
11
1
11
"
Z12" = Z 21
−
Z12(1) Z12( 2 )
Z 01Z 02
( 2)
(1) =
Z11 + Z11 ( Z 01 coth(γ 1l1 ) + Z 02 coth(γ 2l2 )) ⋅ sinh(γ 1l1 ) sinh(γ 2l2 ),
"
Z 22
= Z11( 2 ) −
Z 022
( Z12( 2) ) 2
=
γ
,
Z
coth(
l
)
−
02
2 2
Z11( 2) + Z11(1)
( Z 01 coth(γ 1l1 ) + Z 02 coth(γ 2l2 )) ⋅ sinh 2 (γ 2l2 ) ,
57
,
(4.28)
(4.29)
(4.30)
where transmission line with characteristic impedances Z01, Z02, length l1, l2, and propagation constants γ1,
γ2 [124] are given by
⎡ Z11(1)
[ Z ] = ⎢ (1)
⎣ Z 21
1
⎡ Z ( 2)
[ Z 1 ] = ⎢ 11( 2 )
⎣ Z 21
⎡
⎤
Z 01
Z12(1) ⎤ ⎢ Z 01 coth(γ 1l1
sinh(γ 1l1 ⎥ , and
=
⎥
(1) ⎥ ⎢
Z 01
Z 22 ⎦ ⎢
Z 01 coth(γ 1l1 )⎥
⎦⎥
⎣⎢ sinh(γ 1l1 )
Z 02
⎡
⎤
Z coth(γ 2l2 )
Z12( 2 ) ⎤ ⎢ 01
sinh(γ 2l2 ⎥
=⎢
⎥.
( 2) ⎥
Z0
Z 22 ⎦ ⎢
Z 01 coth(γ 2l2 )⎥
⎢⎣ sinh(γ 2l2 )
⎥⎦
The compensation allows for the uniform distribution of the reflection zeros in the frequency domain.
Each stepped impedance transmission line consists of two λg/8 length transmission lines. The total
electrical length of the transformer is equal to half a wavelength at the center frequency. The return loss
response S22, from (4.27) of the transformer is shown in Figure 4.23. As for comparison, the transformer
discussed in [118] is included. The transformer exhibits six minima (zero reflection) in the spectrum of the
reflection coefficient across the frequency range. The achieved fractional matching bandwidth is beyond a
decade at -20 dB reflection coefficient level with new approach. In addition, the distance between the
minima location Δσ (as shown in Figure 4.23) can be widened to improve low frequency matching by
adjusting the parameters of the structure i.e. step impedance sections (width and length).
0
-10
S22 [dB]
-20
-30
-40
Δσ
-50
2-section transformer
transformer [43]
-60
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency [GHz]
Figure 4.23: Analysis result of output return loss S22 response of the 12.5-50 Ω impedance
transformer shown in Figure 4.24. 6 zero (minima) reflections exist across the frequency range.
For comparison, the transformer shown in [118] is included.
Performance of the broadband impedance transformer is verified with 3D-EM full wave simulator (CST).
The layout is imported from Cadence (in ODB++ format) as shown in Figure 4.24 (a). The port 1 is
terminated with waveguide port (12.5 Ω) and port 2 is connected with 50 Ω SMA connector. A prototype
board is fabricated using Rogers 3-layers PCB (printed circuit board) material which has dielectric
constant εr of 3.6 and a thickness h of 0.762 mm, shown in Figure 4.26 (b). Since port 1 will be connected
58
to a 50 Ω SMA connector in real measurement, the 2-port S-Parameter data of the connector must be
de-embeded for accurate results [126]. The SMA connector 35 is modeled in CST (refer to Figure 4.24).
(a)
(b)
Figure 4.24: a) Layout structure of the transformer imported from Cadence and the simulation is
performed in CST (b) actual prototype board.
waveguide port
PCB with
bottom layer
grounded
discrete
lumped port
S21 [dB]
(a)
Frequency [GHz]
(b)
Figure 4.25 (a) Connector modeling in CST, where waveguide and lumped ports are used, and (b)
Simulated (red curve) and measured results (blue curve) of the connector across the bandwidth.
35
The manufacturer part number of the SMA connector is 73251-1150, from Molex Inc.
59
S21 [dB]
Figure 4.26 and Figure 4.27 are simulated and measured results of the complete broadband transformer.
Insertion loss S21 is acceptable from 10-1800 MHz which is less than 1.5 dB in simulation level. From the
analytical (as shown in Figure 4.23), there is 6 zero reflections, however only 3 and 4 zero reflections
(S22) exist in simulation response of CST and measured data, respectively within pass-band
(10-1800 MHz). As predicted in CST, there is no zero reflection occurrence at center frequency
(1000 MHz). Measured result is acceptable below 1700 MHz (i.e. insertion loss lower about 2 dB), and 4
zero reflection occurred. The results demonstrated are adequate to proof the high efficiency DA concept
although the insertion loss above 1500 MHz is more than 1.5 dB.
Frequency [GHz]
S22 [dB]
Figure 4.26: Simulated vs. measured results of insertion loss S21 of the transformer. Simulation
response of the broadband impedance transformer is performed with CST (line with triangle and
blue curve) and measured result is referred to red line with curve.
Frequency [GHz]
Figure 4.27: Simulated vs. measured results of output return loss S22 of the transformer.
Simulation response of the broadband impedance transformer is performed with CST (line with
triangle and blue curve) and measured result is referred to red line with curve.
60
4.3.4
Measurement Results
In order to experimentally validate the concept of high efficiency DA, a prototype board is fabricated using
Rogers 3-layers PCB (printed circuit board) material which has a permittivity εr of 3.66 and a thickness h
of 0.762 mm. The first layer is used for RF and DC line routing, where all the components placement take
place on top of Layer 1. General layout guidelines e.g. component placements, RF and DC routing,
general layout rules, etc will be explained in Appendix A.
In addition to series gate resistor, a ferrite bead is implemented at drain line together with 33 uF (tantalum
36
capacitor) and 1.8 nF (ceramic capacitor) as a precaution of low frequency oscillation. The DC gate
biasing terminals are bypassed to ground with multiple chip and tantalum capacitors (e.g. 100 pF, 33 nF,
37
10 uF , etc). For the DC feeding lines for final stage is connected to high Q air-wound coil (from Taito
Yuden Inc.), and high Q chip inductors (value of 220 nH) from Coilcraft Inc. The photograph of the high
efficiency DA board is shown in Figure 4.28. The effective DA size area is 27 mm × 24 mm. Two
measurements i.e. R of 12.5 Ω and 50 Ω are performed in the same board outline without repeating
another layout work in Cadence, therefore, point a (in Figure 4.30) will be used to tap the RF output
directly and the transformer section is bypassed when R of 50 Ω is selected. The full transformer section
is utilized when R of 12.5 Ω selected. In other words, two different board designs are used but both
boards have same outline. The drain and gate line elements value for both cases of R are different and
optimized for best performance.
Measured results of small-signal and power performance of 4-section high efficiency DA when terminated
R of 50 Ω, is in Figure 4.29 and Figure 4.30. Each device is fed with 5 V drain supply voltage. Bias
voltage of 0.44 V is applied to each gate resulting in class AB operation, with quiescent current Idq of
~90 mA (10% of Imax). Input return loss S11 is below -10 dB, but output return loss S22 is approx. -5dB
across 10 to 1800 MHz frequency range, as in Figure 4.29. For power performance, as given in
Figure 4.30, the output power of ~500 mW, gain of 8 dB and PAE of 30% are achieved throughout
10 to 1800 MHz frequency range. A good agreement between simulation and measurement result is
obtained.
The measured result of PAE and gain for few case of bias and supply voltage Vg and Vd, respectively is
recorded in Figure 4.31. With high supply voltage (5.4 V) and applied bias close to pinch off (Vg = 0.4 V
where Idq ~5% of Imax), PAE at low frequency is increased by 10% with minimum changes in gain with
comparison to result shown in Figure 4.31. There is no improvement in PAE with supply adjustment. The
performance of ωc has limitation on gate line characteristics.
Due to high insertion loss of the transformer beyond 1.5 GHz the measured results of 4-section high
efficiency DA when terminated R of 12.5 Ω is degraded as the frequency increases. Same supply voltage
and bias voltage is applied to each gate of the transistor (as applied for the case of R = 50 Ω). Measured
results of the power performance of 4-section high efficiency DA when R of 12.5 Ω, is shown in
Figure 4.32. At low, frequency, output power of ~700 mW, gain of 10 dB and PAE about 38% is achieved.
At higher frequencies e.g beyond 1.4 GHz, the performance degraded.
It is necessary to achieve a good performance of the broadband impedance transformer in measurement
level in order to demonstrate best result of efficiency (as shown in Figure 4.32, where PAE > 40% in
simulation level). This proves that the PAE >38% at low frequency with R of 12.5 Ω in measurement. The
efficiency is more than 30% is recorded across the bandwidth operation. It is strong evident from the
measurement results that the concept to achieve high efficiency is well demonstrated. Nevertheless, the
DA performance at higher frequency operation can be improved further with transformer optimization.
36
The capacitors are referring to 600S Series Ultra-Low ESR, high Q microwave capacitors, from ATC Inc. Other capacitors are the
series is 545-L Ultra-broadband high Q capacitors, from Murata Inc.
37
The tantalum capacitor part number is T491D22K016AT, from KEMET Inc. The rated voltage is 16 V @85 °C.
61
+VE
GND
RFout
RFin
Transformer
section
a
24 mm
27 mm
74 mm
RFin
Vg1 Vg2 Vg3 Vg4
Figure 4.28: Photograph of the high efficiency DA prototype board. The terminal a will be tap when
R of 50 Ω output or transformer will be used if R is 12.5 Ω. The effective DA size area is
27 mm × 24 mm.
20
S-Parameter [dB]
0
-20
-40
-60
S11
S22
S21
S12
-80
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency [GHz]
Figure 4.29: Measured versus simulated results of small-signal S-parameters across frequency
range of 10 to 1800 MHz when terminated R of 50 Ω. The straight line is simulated and dotted line
is referred to measured results.
62
P o u t [d B m ], G a in [d B ] & P A E [% ]
50
Pout
PAE
Gain
S i 4
40
30
20
10
0
0
200
400
600
800 1000 1200 1400 1600 1800
Frequency [MHz]
Figure 4.30: Measured versus simulated results of PAE, output power (or Pout) and gain across
frequency range of 10 - 1800 MHz when terminated R of 50 Ω. The straight line is simulated and
dotted line is referred to measured results.
Pow er [dBm ], PAE [% ]
50
40
PAE
30
20
Gain
10
0
0
200 400 600 800 1000 1200 1400 1600 1800
Frequency [MHz]
Figure 4.31: Measured results of PAE and gain for 3 different cases when terminated R of 50 Ω.
The straight line denotes Vg = 0.44 V and Vd = 5 V, the dashed line is referring to Vg = 0.4 V and
Vd = 4.6 V, and straight line with triangle is referring to Vg = 0.44 V and Vd = 5.4 V.
63
P out [dB m ], G ain [dB ] & P A E [% ]
50
Pout
PAE
Gain
S i 4
40
30
20
10
0
0
200
400
600
800
1000 1200 1400 1600 1800
Frequency [MHz]
Figure 4.32: Measured versus simulated results of PAE, output power (or Pout) and gain across
frequency range of 10 to 1800 MHz when terminated R of 12.5 Ω. The straight line is simulated and
dotted line is referred to measured results.
4.4 Dual Fed DA with Termination Adjustment
4.4.1
Motivation
In conventional DA, current combining efficiency at the drain line is poor due to the fact that the current
splitting on the drain line into two branches forming waves traveling towards the load termination, and
waves traveling towards the dummy termination. The tapered drain line DA [11], [12], [83], [91] eliminates
the drain line reverse wave by suitable tapering of the drain line impedance. Dual fed distributed amplifier
(DFDA) topology proposed by Aitchison et al. [127] – [129], allows efficient power combining at the load
termination. Similar technique by realizing Lange coupler and Wilkinson combiner at the input and output
of the DA to improve output power, gain and PAE have been shown by D’ Agostino and Paoloni
[130] - [132]. An approach by [129] showed efficiency improvement by reducing backward wave
propagation at the drain transmission line. The approach by [133] – [134] investigated when the microstrip
line periodically loaded with short open-circuit stubs can be used in place of transmission line to reduce
the size.
This section discusses on the DFDA with termination adjustment which demonstrated remarkable
bandwidth-efficiency improvement over the conventional DA. Instead of lumped transmission line,
discrete approach LC components are utilized and followed by selection of an optimum resonance
frequency of the splitter/combiner [135]. The concept is demonstrated experimentally, where output
power of ~28 dBm and gain of 10 dB, covering moderate bandwidth (100-800 MHz), and PAE >20%, with
low DC supply voltage [23]. The approach is very cost effective method and significant
efficiency-bandwidth improvement is demonstrated compared with the conventional DA.
4.4.2
Principle Operation
The conventional DA consists of input port on one side of the gate line and output port on the opposite
side of the drain line. In basic DFDA, the unused gate and drain ports, which known as dummy
termination will be terminated in appropriate characteristics impedances. The two ports of the gate line
are simultaneously fed and both end of the drain line are assumed as output ports. In this work, the
termination of the DFDA is modified, where remarkable bandwidth extension is possible with optimum
impedance termination selection at both end ports of the gate line [23], as shown in Figure 4.33.In similar
64
manner, by adjusting the termination impedance at drain line, efficiency is maximized over the entire
bandwidth range.
Under linear conditions super-position will apply to its operation and it follows that the output due to
forward gain from the left to right gate input signal will appear at the right hand drain port and similarly the
output due to forward gain from the right to the left gate input signal will appear at the left hand gain port
[129]. These two output signals can be combined to give the total output power. The reverse gain must
also taken into account, and, if the phase of the splitter/combiner is appropriate the currents due to
reverse gain flow out of the same output port and added vectorially to the forward gain [128].
It is explained by [131] that if the both terminations end ports are terminated with an appropriate
impedance values, i.e. higher than Z0, gain improvement is achieved while maintaining the same device
structure. D’ Agostino and Paoloni have demonstrated significant output power, gain and efficiency
improvement over conventional DA applying Wilkinson 38 [131] and Lange coupler 39 [130]. Nevertheless,
this work is focused to improve the bandwidth-efficiency response over conventional DA with modified
DFDA. Beyer et al. has shown analytically that the gate line attenuation αg is more sensitive to frequency
response than the drain line attenuation αd [4].
input
Termination
adjustment
Termination
adjustment
output
DA
Figure 4.33: Schematic diagram of DFDA with termination adjustment [23].
The proposed concept in this work provides optimum impedance at both ends of DA gate line to extend
bandwidth response. With reference to Figure 4.34, Za(ω) = Ra(ω) + jXa(ω) and Zb(ω) = Rb(ω) + jXb(ω), can
be defined as Thevenin impedances for the driving sources ea and eb, respectively at both ends of the DA
gate line DA. Figure 4.34 can be simplified to Figure 4.35 (a). Neglecting eb as shown in Figure 4.35 (b),
voltage V1 can be expressed as
V1 =
ea
,
Ra (ω ) + jX a (ω )
+1
Z OT (ω / ωc )
(4.31)
where) Z OT (ω / ωc ) represents T-section constant-k LC network terminated with matched characteristic
impedance [28]. Note that ωc = 1 / Lg C g , and known as line cut-off frequency.
38
Wilkinson was published by E. J. Wilkinson in 1960 [136], this circuit finds wide use in RF communication systems utilizing
multiple channels since the high degree of isolation between the output ports prevents crosstalk between the individual channels.
39
The Lange coupler is four port, interdigitated structure developed by Dr. Julius Lange in 1969 [139]. The coupling properties are
derived from closely spaced transmission lines, e.g. microstip lines.
65
Za(ω)
Lg/2
V1
Lg
Lg
V2
Vk
Lg/2
Zb(ω)
+
+
ea
Cg
-
Cg
eb
Cg
-
Figure 4.34: Termination adjustment is placed at both end of the input of DA gate line to provide
efficient gate line adjustment over wide frequency range.
Lg/2
+
Za (ω)
ea
Za(ω)
Lg/2
V1
Zb (ω)
eb
Cg
-
V1
+
-
+
ea
(a)
ZOT
-
(b)
Figure 4.35 (a): Simplification of Figure 4.36 and (b) exclusion of eb.
Expression (4.31) can be investigated to gather the V1 behavior over frequency. Assuming ea is set to
V1 = 1∠0° V, an optimum Xa(ω) can be numerically determined for various cases of Ra(ω). V1 in
magnitude is plotted in Figure 4.36, as it can be noticed, the magnitude can be increased over wide
frequency range with proper selection of Ra(ω) + jXa(ω).
Ra=25 Ω, Xa=6 Ω
Bandwidth
extension
mag(V1)
Ra=30 Ω, Xa=4 Ω
Ra=40 Ω, Xa=2 Ω
Ra=50 Ω, Xa=0 Ω
ω /ωc
Figure 4.36: Voltage V1(ω) over normalized frequency (ω /ωc) with proper selection of Ra(ω) + jXa(ω).
Superposition can be now applied to Figure 4.35 (a) considering also eb (and Zb), and the total resulting
voltage V1(ω) is expressed by
66
L
L
Z t ea
Z t eb
,
V1 = L
+ R
Z t + jωLg / 2 + Z a (ω ) Z t + jωLg / 2 + Z b (ω )
where Z t L =
jωLg / 2 + Z b (ω )
1 − ω / 4ωc + jωC g Z b (ω )
2
2
and Z t R =
(4.32)
jωLg / 2 + Z a (ω )
1 − ω / 4ωc + jωC g Z a (ω )
2
2
.
For equal injection at both ends of gate line, ea = eb, the voltage response V1(ω) from (4.32) can be
widened over wide frequency range in similar way by terminating optimum Za(ω) and Zb(ω). In the
following section, bandwidth-efficiency response of the modified DFDA with non-linear device model will
be discussed.
Termination impedance adjustment Za(ω) and Zb(ω) are accomplished by tuning the resonance frequency
fo of Wilkinson splitter at gate line input. Termination adjustment network is realized with Wilkinson splitter
approach. The splitter offers broad bandwidth and equal phase characteristics at each of its output ports
[131]. The splitter employs λ/4 transmission line sections at the design center frequency, which can have
unrealistic dimensions at low RF frequencies, where the wavelength is large [137]. Due to size
constraints, lumped-element equivalent network replacing the λ/4 transmission line would be preferable,
and is shown in Figure 4.37 (a). This network is equivalent to the original only at the center frequency fo.
Consequently, the expected performance (insertion loss, return loss, isolation, etc.) should be similar to
that exhibited by the distributed-form divider for a narrow bandwidth centered in fo, wide enough for most
applications. The “π” LC equivalent networks exhibit a low-pass behavior, refer to Figure 4.37 (b),
rejecting high frequencies, while the response of the classical splitter repeats at odd multiples of the
center frequency (3fo and 5fo, mainly) [137].
1 GHz microstrip Wilkinson splitter or combiner could occupy about 6 cm2 on FR-4 PCB, while this
lumped-element version occupies less than 1 cm2. Lumped-element circuits with high-Q than distributed
circuits have the advantage of smaller size, low cost, and wide bandwidth characteristics [140]. The
element values are given by the following equations
C=
1
,
2πf o Z o
(4.33)
L=
Zo
,
2πf o
(4.34)
where Zo and fo are characteristic impedance and resonance frequency of the lumped elements,
respectively as shown in Figure 4.37 (b).
λ/4 length
L
C
(a)
C
(b)
Figure 4.37: Lumped element π-section (a) transmission line (b) lumped elements.
67
To investigate the output drain line of the modified DFDA, Figure 4.38 will be considered. Forward current
(Io1 and Io2), summing in phase on the correspondent output ports are considered [131]. For simplicity, the
circuit is analyzed at low frequencies. By assuming that the input voltage of each gate line is Vi /√2, output
current towards each output port is expressed as
I oi =
nRds
V
gm i ,
(nZ 0 o + 2 Rds )
2
i = 1,2 ..n ,
(4.35)
where n is the number of FETs, Rds is the drain-source resistance of the active devices, gm is their
transconductance and Z0o is the load impedance of the output ports (Z0a and Z0b). The total output power,
Pout computed as the sum of the contribution from Io1 and Io2, is given by
Pout =
1
1
2
2
I o1 Z 0 a + I o 2 Z 0b ,
2
2
(4.36)
and when Z0a = Z0b = Z0, Pout can be simplified as below
2
Pout =
2
n 2 Rds2 Z 0
2 Vi
.
g
(nZ 0 + 2 Rds )2 m 2
(4.37)
The power delivered from the input source Pin, is
Pin =
1 Vi 2
,
2 Zo
(4.38)
where Vi are the supply voltages and Zo is gate line characteristic impedance. The overall gain of the
topology, G is given by
2
G=
Pout
n 2 Rds2 Z 0
=
g m2 .
Pin (nZ 0 + 2 Rds ) 2
(4.39)
From (4.39), when increasing Z0, higher gain and output power can be obtained. Unfortunately, the
correspondent degradation of the output reflection is a critical limitation [131]. The gain as a function of
the output loads Z0a and Z0b for different number of FETs (n = 2, 3, 4) and the correspondent return loss
are discussed in [131]. One can conclude from [131] that right selection of Z0a and Z0b for chosen n, will
lead to optimum power performance without trading off output return loss. In this work, it is worth while to
select the fo of the drain line, to improve the output matching over the entire bandwidth.
68
IO2
IO1
Z0b
Z0a
Ld
Ld/2
Cds1
Lm
Cm
Ld
i1
Ld/2
Rds1
i2
Lm
Cdsn
Cds2
Rds2
in
Rdsn
Cm
Figure 4.38: Theoretical circuit analysis of the drain of the modified DFDA [131].
4.4.3
Design Example of DFDA with termination adjustment
The basic design goal of the work is to achieve high efficiency for SDR driver PA applications. The power
40
operation is ~27 dBm. Therefore, medium power device i.e. LDMOS n-type MOSFET packaged device
is suitable. The low DC supply operation is required for the device, which typically is about 7.5 V.
Break-down voltage Vbk of the device is ~25 V, which is close to the computation value from (3.47). The
drain loading effect of the device is not significant, but, however Xopt(ω) is important since it determines
the drain line cut-off frequency ωc. The effective device input and output capacitance is Cin = 14 pF and
Cout = 8 pF, respectively are extracted by means of device modeling (with inclusion of packaged
properties). Therefore, effective drain line elements i.e. Li are synthesized by means of (3.48) to form
desired ωc (~800 MHz). The dummy drain termination is eliminated to improve the efficiency performance.
Design of the modified DFDA is very much similar to that of high efficiency DA (as discussed in
section 4.3.2), and additionally termination adjustment network is implemented. Hence, the method of
synthesizing a DA comprises the steps of device selection, determining an appropriate topology,
synthesizing gate/drain line elements from device packaged values, etc are applied. High-Q discrete
inductors and capacitors from Coilcraft Inc. and Murata Inc. are selected for the reason of lower ESR
value and minimum part tolerance. The gain of the amplifier increases with additional devices until
optimum number of devices at given frequency is reached [4]. Any device added beyond this optimum
number is not driven sufficiently to excite the signal in the drain line which will induce attenuation in the
extra section of the drain line. Based (3.37), nopt is 3.26 for RD01MUS1 device. Due to this, 3 devices
have been used in our design.
Inductances of gate and drain lines could be determined from the value of the line image impedance and
ωc. As for RF standard, gate and drain line image impedance are set to 50 Ω. In order for the currents on
the drain line to interfere constructively (add in phase) the phase shift per section on gate and drain lines
must be equalized. The phase velocities synchronization between gate and drain line is achieved by
adjusting the inductance value of the gate line (the capacitively coupled technique, where discrete
capacitor in series form to each gate of the transistor is not implemented). m-derived serves wideband
image impedance image termination and placed at both end of gate and drain lines. m-derived half
section designed with m = 0.6 for best flatness across the bandwidth [28]. For the termination adjustment
network, L and C are selected according to (4.33) and (4.34), where an optimum fo and Zo will be
identified in simulation analysis. For convenience reason, Zo is set to 70.7 Ω, but fo will be determined.
The modified DFDA topology is shown in Figure 4.39.
40
The device part number is RD01MUS1, from Mitsubishi Corp., Kanagawa, Japan.
69
Figure 4.40 shows by applying termination adjustment with proper selection of fo at gate line reveal an
improvement of bandwidth although small degradation in gain is expected due to loss of the splitter 41 .
Nevertheless, the gain of the amplifier from low frequency can be boosted with similar way at the drain
line. The fo selection at drain line does not improve the bandwidth performance. As shown in Figure 4.41,
the gain response of the modified DFDA is improved by 200 MHz compared to the conventional DA.
Simulation analysis (with Harmonic Balance) of the modified DFDA with non-linear device and passive
models showed optimum selection of fo (i.e. fo ~600 MHz) lead to bandwidth extension with minimum gain
peaking, refer to Figure 4.40.
Hence, as a guidelines, tuning the fo of the termination adjustment network in the range of less then line
cutoff frequency fc and to be greater the conventional DA center frequency, significant bandwidth
extension is promising over the conventional DA.
output
impedance
termination
adjustment
Ld/2
Q1
Lm1
Ld
Ld
Q2
Ld/2
Q3
Lm2
Cm1
Cm2
Lg/2
Lg
Lg
Lg/2
Lm1
Lm2
Cm1
Cm2
impedance
termination
adjustment
input
Figure 4.39: Modified DFDA having termination adjustment network at both gate and drain lines.
m-derived is terminated at both end of the gate and drain line termination [23].
41
The measured loss of the splitter is characterized approximately 3 dB, over the entire bandwidth.
70
20
10
Gain [dB]
0
-10
-20
-30
conventional DA
-40
gate line adjustment
gate and drain line adjustment
-50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [GHz]
Figure 4.40: Gain response for few cases i.e. conventional DA (blue curve), applying termination
adjustment at gate line (brown curve) and termination adjustment at gate and drain line (red
curve).
20
10
Gain [dB]
0
-10
-20
-30
-40
500 MHz
600 MHz
1000 MHz
900 MHz
700 MHz
800 MHz
-50
-60
100 200 300 400 500 600 700 800 900 1000
Frequency [MHz]
Figure 4.41: Gain vs. frequency for various case of fo tuning. Fine selection of fo ~600 MHz (pink
curve) leads to bandwidth extension with minimum gain peaking.
Simulation performance (with Harmonic Balance) of the 3-section modified DFDA is compared to a
conventional DA. Both topologies used same device, same input and output artificial transmission line,
DC biasing scheme at the same condition (VGS = 2.1V and VDS = 7.8V) and same Pin = 17dBm for both
amplifiers. The resonance frequency fo is selected to 600 MHz. The gain of the conventional DA is
9.5 ± 1 dB whereas for the modified DFDA increased by ~2 dB across 100 to 900MHz bandwidth (refer to
Figure 4.42). PAE for conventional DA is lower than 20% whereas PAE for the modified DFDA is
increased by ~10%, as shown in Figure 4.42.
71
Gain [dB] & PAE [%]
50
Gain
Gain
PAE
PAE
40
- dual fed DA with termination
- conventional DA
- dual fed DA with termination
- conventional DA
30
20
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [GHz]
Figure 4.42: Gain and PAE comparison for modified DFDA and conventional DA having same
input and output artificial transmission line, DC biasing scheme at the same condition (VGS = 2.1V
and VDS = 7.8V) and same Pin = 17dBm).
S-Parameter [dB]
0
-10
-20
-30
S11 - dual fed with termination
S11 - conventional DA
S22 - dual fed with termination
S22 - conventional DA
-40
-50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [GHz]
Figure 4.43: S-parameters comparison for modified DFDA and conventional DA having same input
and output artificial transmission line, DC biasing scheme at the same condition (VGS = 2.1V and
VDS = 7.8V) and same Pin = 17dBm).
The remarkable achievement of the modified DFDA is power-efficiency operation range is tremendously
improved by 200 MHz over conventional DA. S-parameter simulation of the modified DFDA is given in
Figure 4.43, and obviously the input and output return loss are degraded below 600 MHz compared to
conventional DA. Since the tuning resonance frequency of the termination adjustment is 600 MHz, and
the return loss has significant improvement beyond 600 MHz. However, the input and output return loss is
<-5 dB across bandwidth.
72
4.4.4
Measurement Results
In order to experimentally validate the concept of DFDA with resonance adjustment, a prototype board is
fabricated using FR4 42 3-layers PCB (printed circuit board) material which has a permittivity εr of 4.5 and
a thickness h of 20 mils. The photograph of the board is given in Figure 4.44. The first layer is used for
RF and DC line routing, where all components placement take place. The bottom layer is used for solid
RF grounding. General layout guidelines e.g. component placements, RF and DC routing, general layout
rules, etc will be shared in Appendix A.
Measured results of small-signal and power performance of 3-section modified DFDA, are shown in
Figure 4.45 and Figure 4.46. Each device is fed with 7.8 V drain supply voltage. Bias voltage of 2.1 V is
applied to each gate resulting in class AB operation, with quiescent current Idq of ~90 mA (10% of Imax).
Input return loss S11 is below -10 dB, but output return loss S22 is approximately -5dB across
100 to 800 MHz frequency range, as in Figure 4.45. It is possible to provide optimum fo at drain line to
improve further S22. There is minimum gain peaking observed in small signal performance although it is
seen in simulation result.
As for the power performance, as given in Figure 4.46, the output power of ~28 dBm, gain of 10 dB and
PAE of >20% are achieved throughout 100 to 800 MHz frequency range. As for the comparison,
conventional 3-section DA having same input and output line impedance, and same DC biasing scheme
are built and measured. Note that PCB properties and layer structure are identical. From 4.46,
remarkable efficiency performance is achieved with the new topology while reasonable bandwidth is
extended. Average PAE of 15% is improved across the bandwidth. A good agreement between
simulation and measurement result is obtained.
RFout
+Vgate
+Vdrain
32 mm
GND
GND
32 mm
RFin
Figure 4.44: Photograph of the modified DFDA prototype board. The effective DA size area is
32 mm × 32 mm. The termination adjustment network is located within yellow color circle, and DA
in red color circle.
42
FR4 is the grade designation for glass reinforced epoxy laminate sheets PCB, and made from woven fiberglass. The εr is 4.3 @
1 GHz, and suitable for application below 1 GHz.
73
40
S-param eter [dB]
20
0
-20
-40
S21- Simulated
S22 - Simulated
S12 - Simulated
S11- Simulated
-60
S21- M easured
S22 - M easured
S12 - M easured
S11- M easured
-80
0
0.2
0.4
0.6
Frequency [GHz]
0.8
1
Figure 4.45: Measured versus simulated results of small-signal S-parameters across frequency
range of 100 to 900 MHz
P A E [% ] / G ain [dB ]
70.0
PAE - modified DA (measured)
Gain - modified DA (measured)
PAE - conv. DA (measured)
Gain - conv. DA (measured)
PAE - modified DA (simulated)
Gain - modified DA (simulated)
60.0
50.0
40.0
30.0
20.0
10.0
0.0
0
200
400
600
Frequency [MHz]
800
1000
Figure 4.46: Measured versus simulated results of PAE and gain across frequency range of
100 - 900 MHz.
Table 4.3 summarizes power and PAE performance over the bandwidth from 100-800 MHz for the
state-of-art DA realizations (this works adopts low DC supply voltage). This work, [115] and [138]
demonstrated operating frequencies for the 100-800 MHz range, while work in [83] is operating in the
bandwidth 10-800 MHz. From the table below, this work demonstrated the highest output power with low
DC supply voltage with remarkably good efficiency performance.
74
PAE
20-45%
Tan et al.
[115]
18-27%
Power
28.3 dBm
30dBm
27.4 dBm
26 dBm
DC
supply
device
7.8 V
7.2 V
6.5 V
4.5 V
LDMOS
LDMOS
HBT
pHEMT
section
3
3
3
4
This work
Olson et al.
[138]
20-47%
Narendra et al.
[83]
28-30%
Table 4.3: Summary performance of power and PAE over the 100-800 MHz for the state-of-art of
DA realizations.
4.5 Conclusion
It is important to note that to achieve high DA efficiency performance, the multi current sources must be
combined to a single load by presenting an optimum virtual impedance to each current source in two
directions (Zu(k) and Zr(k)). The generalized design equations are developed in section 4.2, are useful to
determine Zu(k)/R and Zu(k)/R. Obviously, to remain R of 50 Ω (and to avoid additional impedance
transformation), magnitude and phase properties of the current source (or transistor) must be adjusted to
achieve lower Zu(k). The adjustment can be made according to designer’s need, complexity of the design
circuit, etc. It is still possible to improve efficiency (while remaining R of 50 Ω) with various ways e.g.
non-uniform gate line design, device periphery, etc, which is an attractive solution for MMIC (monolithic
microwave integrated circuit) approach. Nevertheless, Zu(k) can be reduced further with lower value of R,
but as consequence, low insertion loss transformer design must take places. Measurement results
showed PAE > 30% is achieved across the operating frequency range (10 - 1800 MHz). A broadband
impedance transformer employing parallel coupled line approach is adopted. As an important point, one
should note that the design concept presented in this work provides appropriate guidelines to maximize
DA efficiency.
A novel topology of dual fed DA including input and output splitter realized by lumped elements, and with
the termination adjusted for the optimum power performance with low DC supply voltage is presented.
The termination adjustment is accomplished by relevant improvement obtained in comparison to the
conventional DA topology demonstrates the effectiveness of the topology. The output power of ~28 dBm,
covering moderate bandwidth (100-800 MHz), and PAE >20%, and using 7.8 V DC supply voltage is
demonstrated experimentally. The good agreement of the simulations with the realized amplifier
measurement confirms that also in the experimental phase the amplifier is a real improvement to be used
for the wideband frequency band power amplifier with low DC supply voltage.
75
Chapter 5.
Stability Analysis in Distributed Amplifiers
Hardware fabrication cost of microwave circuits, especially power amplifier circuit is expensive, therefore,
it is necessary to have good technique that allow one to correctly predict the behavior of the microwave
circuits with the purpose of detecting and correcting possible problems during the design stage. The basic
principle of stability analysis with the intent of understanding the strategies that will be adopted for the DA
design.
In this chapter, a procedure that includes both small-signal and large-signal stability analyses to detect,
and eliminate undesired oscillations in DA, including parametric type is discussed. The stability analysis is
based on determining the poles of a closed-loop transfer function resulting from linearizing the system
around a steady state regime. The origin of the instability is investigated and suitable stabilization circuit
is implemented in the high efficiency DA with minimum degradation of power performance.
5.1 Motivation of Stability Analysis
Originally, Rollet [141] deduced the basic results for the stability of linear two port RF amplifiers as a
function of parameters Z-, Y-, G-, or H-parameters of the network. However, Woods shows simple
examples of circuits with negative resistances that do not fulfill the Rollet condition and whose stability
cannot be correctly deduced using the conditions [142]. Platzker also paid attention to this fact illustrating
real examples of circuits with various active elements in which using the K factor led to erroneous
conclusions [143]. Low frequencies instabilities due to bias circuits cannot be detected using K-factor
[144]. Study by [144] showed that K-factor is not sufficient to analyze stability criteria of multistage
amplifiers due to the fact that possible feedbacks between stages are not taken into account. In power
combining structures with n transistors in parallel, n possible modes of oscillation exist [145], [146], and
K-factor only allows detecting of even mode of oscillation. As an alternative, in [144] they propose an
analysis of the K factor capable of detecting odd mode oscillations using an ideal transformer that forces
the odd mode of oscillation in the circuit.
Ohtomo proposes a rigorous method for evaluating the stability of a DC solution in microwave circuits with
multiple active devices that can contain multiple feedback loops [147]. The method is valid for the
detection of odd and even mode oscillations and can be applied to any linear or nonlinear circuits with a
linear equivalent around the bias point. Centurelli et al. [148], [149] present the necessary and sufficient
conditions for the stability of circuits with multiple active devices in agreement with the procedure
proposed by Ohtomo [147] but also guaranteeing a stability margin in circular regions around complex
terminations. Ohtomo’s method is based on the Nyquist criterion and requires observing the 2N transfer
functions associated with each port. However, Centurelli et al. define the margins of gain and phase that
allow determining the stability of the circuit.
Kassakian and Lau emphasize the possibility of the appearance of odd mode oscillations with voltage
combining structures [150]. Postulating a priori the mode of oscillation of the circuit and applying the
Routh-Hurwitz [151] criterion to the zeros of the characteristic equation an odd mode oscillation in a
power amplifier can be detected. Freitag proposes a method for the detection of odd mode oscillations
based on the representation of Z-parameters of the circuit [146]. It identifies the different modes of
operation of the multistage amplifiers. The drawback of this method is characteristic matrix of the system
is needed therefore not suitable to implement for commercial simulators.
Ramberger and Merkle [152] apply Ohtomo method [147] to circuits with voltage combining structures.
Instead of applying the method to the complete circuit, they use an equivalent circuit with a single branch
which remarkably reduced the simulation time. Costantini et al. [153] also propose a method that allows
the detection of odd and even mode oscillations, and the circuit must be analyzed using as many
equivalent circuits as modes of oscillation that can possibly exist in the circuit.
76
5.2 Stability Analysis Methods
In this section, few stability analyses i.e. K-factor of two-port network, feedback and NDF factor, and
finally pole-zero identification method will be discussed. This will give good understanding.
5.2.1
K-factor stability of a two port network
A two port network is unconditionally stable if no combination of passive source and load impedances
exists that can cause the circuit to oscillate. For it, it is a necessary condition that the real part of the
immittance (impedance or admittance) observed at the input of each of the ports remains positive with
any passive termination that is connected to the other port. This is translated in the following conditions
from [132], where
K=
2 Re(γ 11 ) Re(γ 22 ) − Re(γ 12γ 21 )
γ 12γ 21
≥ 1,
(5.1.a)
Re(γ 11 ) ≥ 0 ,
(5.1.b)
Re(γ 22 ) ≥ 0 ,
(5.1.c)
where γij represents the element (i, j) of any of the Z-, Y-, G-, or H-parameter matrices.
(5.1) can be rewritten as a function of the S-parameters, which are more adequate for describing radio
frequency and microwave circuits, obtaining, in this manner, a set of conditions equivalent to (5.1) for
unconditional stability [141]. If in the whole range of frequencies for which the device shows the following
equations are fulfilled
1 − S11 − S 22 + Δ s
2
K=
2
2
>1,
2 S12 S 21
(5.2.a)
together with one of the following oscillation conditions,
Δ s = S11S 22 − S12 S 21 < 1 ,
(5.2.b)
B1 = 1 + S11 − S 22 − Δ s > 0 ,
2
2
2
(5.2.c)
B2 = 1 − S11 + S 22 − Δ s > 0 ,
2
2
2
(5.2.d)
1 − S11 > S12 S 21 ,
(5.2.e)
1 − S 22 > S12 S 21 ,
(5.2.f)
2
2
The unconditional stability of the two port network is guaranteed only if the Rollet condition is fulfilled.
That is to say, whenever the unloaded circuit does not have poles in the right half plane of the s-plane.
The condition for K and the auxiliary conditions can be replaced by a single figure of merit μ [154]. The
new condition for unconditional stability is
77
μ=
1 − S11
2
S 22 − S11* Δ + S 21S12
> 1,
(5.3)
whenever the Rollet condition is fulfilled. The parameter μ, in addition to evaluating the unconditional
stability of a two port network, allows estimating its degree of potential instability, since it can be
geometrically interpreted as the minimum distance between the origin of the unit Smith chart and the
unstable region. Nevertheless, the parameter μ has not been able to replace the K factor that continues
to be mainly used by microwave circuit designers.
If the conditions (5.1), (5.2) or (5.3) are not fulfilled at all the frequencies it is said that the two port
network is conditionally stable. It is important to study the impedances that, connected to the input or
output, can make the circuit oscillate. That is to say the source ZS and load ZL impedances for which
Γin > 1 ,
(5.4)
Γout > 1 ,
(5.5)
where Γin and Γout are the reflection coefficients at the input and output of the two port network
(Figure 5.1) that are given by the following expressions:
Γin = S11 +
S12 S 21ΓL
,
1 − S 22 ΓL
Γout = S 22 +
(5.6)
S12 S 21ΓS
,
1 − S11ΓS
(5.7)
[S]
68 m
mΓS
Γin
Γout
ΓL
Figure 5.1: Two-port network terminated with input and output impedances.
In a circuit that is not unconditionally stable it is necessary to carefully select the load impedances to
avoid the presence of undesired oscillations. For it, it is convenient to find the limit between the unstable
and stable region. At the input, the location of the points of ΓL that make Γin (ΓL ) = 1 can be drawn in the
plane of the reflection coefficient of the load.
characterized by its center CL,
The result is the output stability circle [141] that is
78
CL =
*
S 22
− Δ*S S11
S 22 − Δ S
2
2
,
(5.8)
and its radius rL ,
rL =
S12 S 21
S 22 − Δ s
2
2
,
(5.9)
It contains the values of ΓL that are found at the limit of the stability region. To find the limit between the
unstable and the stable region, the location of the points of ΓS that make Γout (ΓS ) = 1 can be drawn in
the plane of the reflection coefficient of the source. The result is the input stability circle that is also
characterized by its center CS,
CS =
S11* − Δ*S S 22
S11 − Δ S
2
2
,
(5.10)
and its radius rS,
rS =
S12 S 21
2
S11 − Δ s
2
.
(5.11)
It contains the values of ΓS that are found at the limit of the stability region. Equations (5.8), (5.9), (5.10)
and (5.11) determine the limits of the stability region, but it needs to be determined if the stable region is
in the interior or outside the stability circles. In analyzing the output stability circles we will have ⏐Γin⏐ < 1
and on the other side ⏐Γin⏐ > 1. If the load impedance is in the center of the Smith chart (ΓL = 0), from
(5.6) it is obtained that ⏐Γin⏐ = S11. In this way, if ⏐S11⏐ < 1, the center of the Smith chart is in the stable
region and load ⏐S11⏐ > 1, then it is in the unstable region. Also, the input stability circles delimit the
regions for ⏐Γout⏐ < 1 and ⏐Γout⏐ > 1 is fulfilled. From (5.7) it is deduced that if ⏐S22⏐ < 1, the center of
the Smith chart, that corresponds to ZS = Z0 and ΓS = 0, is in the stable region and if ⏐S22⏐ > 1 is in the
unstable region.
5.2.2
Feedback and NDF factor
Platzker et al. [134] established the inconvenience of applying the Rollet stability criterions [141] in the
linear networks that present a pole in the right half plane of the complex plane. In addition, these authors
proposed a technique to determine whether a circuit has or does not have a pole in the right half complex
plane before applying the Rollet stability criterion [155]. This technique is based on the diagram or
location of a normalized determinant function (NDF) of the circuit in the complex plane and is a
generalization of the works of Bode [70] to circuits with multiple active elements.
79
Taking into account the multiple internal feedbacks that are produced in a circuit with various active
elements, the study of stability can be carried out using the theory of feedback systems [70] and thus
overcoming the inherent limitations of the K factor. The Bode theory [70] deals with the systems with a
single feedback loop where the active element is included in a passive feedback network. Figure 5.2
shows the block diagram of a system with a single feedback loop.
∑
Ve
+
Vs
A
+
β
Figure 5.2: Block diagram of a system with a single feedback loop.
The transfer function of the complete system can be expressed in the following form
G=
Vs
A ,
=
Ve 1 − Aβ
(5.12)
Function Aβ is called the open loop transfer function and is obtained in absence of the input voltage
(Ve = 0) simply cutting the feedback loop, introducing a unit amplitude signal at the input of the active
element, and measuring the return signal at the break point (Figure 5.3).
∑
0
+
Vs
Aβ
1
A
+
β
Figure 5.3: Obtaining the open loop transfer function.
In Bode’s works, functions −Aβ and 1− Aβ are designated as return level and return difference or
feedback factor, respectively.
RR = − Aβ , F = 1 + RR = 1 − Aβ .
(5.13)
To measure the open loop transfer function of a circuit with a single active element like the one in
Figure 5.3, the dependent source i = gmvin must be replaced by an equivalent dependent source of an
auxiliary generator vext of variable frequency, as in Figure 5.4.
80
V’
Ig
+
Vext’
-
gmVext’
RL
Rg
Figure 5.4: Obtaining the return level in a circuit with a single active element.
The return level associated with the voltage dependent current source is defined as
RR = −
V'
,
Vext
(5.14)
and can easily be obtained using the scheme given in Figure 5.4 .
The feedback factor F with respect to a transfer parameter gm can be expressed as [156]:
F=
Δ
,
Δ0
(5.15)
where Δ represents the determinant of the complete circuit (including the terminations of each port) and
Δ0 represents the determinant of the passive network that results from setting the only dependent source
of the circuit to zero (gm = 0). Any matrix of Y-, Z- or H-parameter that describe the linear circuit can be
used to calculate the determinants Δ and Δ0 .Applying the Nyquist criterion to the function F
F = 1 + RR = 1 −
V'
,
Vext
(5.16)
the stability of the closed loop circuit can be determined.
For the correct application of the Nyquist criterion it is important to emphasize the denominators of
functions Δ and Δ0 are the same; therefore they cancel each other out. In this way, the zeros of function
F are the zeros of the characteristic determinant of the system or, in other words, the poles of the closed
loop transfer function. Also, since Δ0 is calculated from a passive circuit [156], it cannot have zeros with a
real positive part, hence function F cannot have poles with a real positive part by analysis. On the other
hand, since Δ(σ + jω) and Δ0 (σ + jω) are of the same order, when ω → ∞ or σ → ∞ function F tends to
one. Lastly, since the response of the circuit is a real function, F(−jω) = F*(jω).
In this manner, since function F does not have unstable poles and its zeros represent natural frequencies
of the circuit, if the Nyquist trace of function
F = Δ( jω )
Δ 0 ( jω )
,
(5.17)
81
varying from 0 to ∞ does not encircle the origin, the system is stable. On the contrary, the appearance of
an instability is characterized by the clockwise encirclement of the Nyquist trace around the origin. In this
case, the frequency crossing the negative real axis provides an approximation of the starting frequency of
the oscillation [157].
5.2.3
Pole-zero identification method
Pole-zero identification method is based on a transfer function approach, where the function of the
system linearized about the steady state solution is obtained to extract the stability informations [158]. By
introducing a small signal RF current generator iin in node n of an electric circuit, shown in Figure 5.5,
there exists a direct equivalent between the circuit and the system given in (5.18). To obtain the
frequency response of the circuit required for stability analysis of a DC solution it is enough to introduce a
small signal RF current generator iin in any node of the circuit fed solely by the bias sources. The
frequency response H(jω) is obtained by means of a linear analysis of the impedance observed by the
current generator to its operating frequency fs while the frequency fs is being swept [158].
H ( jω s ) =
vout
Z 2n
Z nZ n
=
= n 1 2 n = Z1n Z 2n = Z Tn ( jω s ) .
iin 1 + Z n 1
Z 2 + Z1
2
n
Z1
(5.18)
n
+
iin (ωs)
n
Z1
n
Z2
-
Figure 5.5: General diagram of an electric circuit with a current generator in parallel. The H(jωs) is
determined as the ratio of vout/iin.
This is a general result, thus the frequency response in any node n of the linearized circuit can be easily
calculated by introducing a small signal current generator in that node n and measuring the impedance
ZTn ( jω s ) observed by the current source as the frequency ωs of the current source is swept. It is
important to emphasize that, as a result of its parallel connection, the introduced current generator will not
have influence on frequencies different from its own operation frequency. Frequency response
associated with the current source generator that display a low impedance path to ground are not suitable
for the analysis, but introducing voltage generator in that branch to determine admittance YTm(jωs) is
rather effective [157], refer to Figure 5.6.
The next step of the technique of stability analysis consists in extracting the information relative to the
stability from the frequency response of the circuit. In the case of DC stability analysis as in the large
signal, the information is contained in the denominator of the transfer function associated to the frequency
response is obtained. Furthermore, in either of the cases there is no guarantee that the associated
transfer functions lack unstable zeros, which is the reason why the simplified Nyquist analysis is not, in
general, valid [156]. The utilization of system identification techniques like the general methodology for
the extraction of the information relative to the stability from the frequency response of the circuit is
proposed. The techniques of system identification allow one to obtain the transfer function H(s)
associated to the frequency response H(jω) of the circuit.
82
n
+
-
iout
vin (ωs)
Y1n
Y2n
Figure 5.6: General diagram of an electric circuit with a voltage generator in series. The H(jωs) is
determined as the ratio of vout/iin.
Nz
H ( jω )
identification
process
H (s) =
∏ (s − z )
i
i =1
Np
,
(5.19)
∏ (s − p )
i
i =1
where zi and pi are the zeros and poles respectively of the transfer function H (s) of the system.
Once the poles and zeros of H(s) are obtained, we proceed to the analysis of the poles to determine the
stability of the analyzed steady state. In the case of a frequency response associated with a DC state of
the circuit, the poles of the identified transfer function are adjusted to the eigenvalues of the Jacobian
matrix [159]. In the case of a frequency response associated with a periodic state, the poles correspond
to the Floquet exponents of the system [158]. Therefore, in both cases, the existence of a pair of
conjugate complex poles with a positive real part in the transfer function H(s) predicts the instability of the
system. In other words, it indicates that the analyzed steady state is unstable and that an oscillation of
increasing amplitude to an independent spurious frequency is generated. The autonomous oscillation
initiating at ωa is determined by the magnitude of the imaginary part of these poles [159].
43
The identification tools available in Scilab are transfer functions that have an excess pole-zero null,
therefore, the order of the transfer function is equal to the number of poles and the number of zeros. It is
important to emphasize that if we attempt to identify a frequency response with a transfer function order
higher than necessary, good identification results will be obtained. Nevertheless, there will probably be
pole-zero quasi-cancellations that can be eliminated using a lower transfer function order [157]. If the
quasi-cancellations are stable, they do not represent a problem, but if they are in the right-half plane, it
will be necessary to verify if a precise identification without the appearance of these quasi-cancellations
can be obtained [157].
5.3 Analysis and Conditions of Stability in DAs
S-parameter of DAs without feedback capacitance Cgd, have been calculated by Niclas et al. [160], and
the analysis of such amplifier become complicated with inclusion of Cgd of an active device. [161] showed
that the occurrence of oscillations in DA (with simplified transistor model) can be root caused to the high
transconductance gm and gate-drain capacitance Cgd of the transistor. Furthermore, the approach
highlighted in [161], where the impedances of the left and right-hand parts of the circuits from any
arbitrary reference plane (i.e. node x, y,.., etc) are not sufficient to illustrate the oscillation phenomenon
due to the fact the line impedances are identical (symmetrical structure), shown in Figure 5.7. However, in
[161], Gamand has explained that origin of the oscillation can be found in the loop constituted by nodes a,
43
Scilab program can be downloaded at www.scilab.org.
83
b, c and d, as in Figure 5.7, and the amplifier tends to oscillate when the gain within the loop becomes too
high.
From the circuit theory we know that oscillation occurs when a network has a pair of complex conjugate
poles on the imaginary axis. If the closed-loop gain in (Barkhusien) has a pair of complex conjugate poles
in the right half plane (RHP), close to the imaginary axis, due to the ever present noise voltage generated
by thermal noise in the network, a growing sinusoidal output voltage appears [36]. As the amplitude of the
noise induced oscillation increases, the amplitude limiting capabilities of the amplifier produce a change in
the location of the poles. To show the origin of the oscillation in basic DA structure associated to the
critical poles, that can be found in the loop constituted by node a, b,.., etc.
y
Ld/2
Rdt
c
Lg/2
RL
Q2
Q1
Rgin
Ld/2
d
a
x
b
Lg/2
Rgt
Figure 5.7: Basic DA structure in two section transistors.
To further the analysis, it is convenient to consider a basic single section DA as a basic feedback
oscillator circuit, and using a simplified transistor model. The transistor is assumed as voltage controlled
current source (VCVS). The real part Rds is included in the model. The basic single section DA and the
simplified transistor model are given in Figure 5.8. The transformation of the single section DA to the
feedback oscillator circuit is shown in Figure 5.9, where a basic Hartley oscillator is formed. Z1(ω) and
Z2(ω) are impedance seen by gate and drain points, respectively as shown in Figure 5.8 (b). In basic
Hartley oscillator, Z1(ω) and Z2(ω) can be replaced with single inductance element, e.g. Lg and Ld,
respectively. For the oscillation to occur, according to [36], the loop resistance must be zero, thus one can
define gain condition as
g m Rds =
Ld ,
Lg
(5.20)
where gm is device trans-conductance and frequency of oscillation ωo is given by
ωo =
1
,
LT Cgd
(5.21)
where LT = Lg + Ld .
Pole-zero identification of a linearized frequency response is used here for stability analysis [158]. By
introducing a small signal RF current generator i(fs) to node Vin of the circuit shown in Figure 5.9. The
84
frequency response H(jω) is obtained by means of a linear analysis of the impedance observed by the
current generator to its operating frequency fs while the frequency fs is being swept.
By selecting Cgd = 2.2 pF, Lg = 8 nH, Ld = 16 nH, Rds = 200 Ω and gm = 10 mS, as an example, fo is
computed from (5.21) and the network oscillate around 694 MHz 44 . Two peaking are occurred in H(jω) as
shown in Figure 5.10 (a), where the unstable poles (with positive peaking and negative slope phase) and
zeroes (with negative peaking and positive slope phase) at 694 MHz and 1.2 GHz, respectively. It is clear
that the critical pole close to imaginary axis is located at 694 MHz, as shown in Figure 5.10 (b).However,
by arranging the gate and drain line to have cut-off frequency fc around 800 MHz and line impedance of
50 Ω, there is no oscillation indication observed.
Z1(ω) Cgd
Ld/2
Lg/2
Z2(ω)
+
Vin
+
gmVin
Cgs
Vout
Rds
Ld/2
Cds
-
-
Lg/2
(a)
(b)
Figure 5.8: (a) Basic single section DA design, and b) simplified transistor model.
i(fs)
Cgd
+
Vin
+
gmVin
Rds
Vout
-
-
Feedback
network
Z2(ω)
Z1(ω)
Figure 5.9: A basic single section DA is transformed to a basic feedback oscillator i.e. Hartley
Oscillator. A small signal RF current generator i(fs) to node Vin.
To understand the origin of the oscillation in DA (having multi-loops), lets consider 2 section DA (from
Figure 5.7), where it can be simplified to Hartley Oscillator configuration (as given in Figure 5.9). The
feedback network Z1(ω) and Z2(ω), respectively is formed by multi-loops arrangement, refer to
Figure 5.11. Z1(ω) and Z2(ω) are strictly rely on the loop associated due to gm2, Cgd2, Lg, Cgs2, Ld, Cds2,
terminations, etc. Important point to be noticed is that the poles are become stable when the primary loop
(in red color, with Cgd2 = 0) and device 2 has very low gm2 effect (or negligible). Although the primary is not
connected, the oscillation is still exists when gm2 is increases to adequate value due to the fact other loops
(in blue color) still present. Few cases are examined.
44
The selective elements are determined based on constant-k network to show the oscillation frequency below 800 MHz (within the
passband).
85
(a)
Critical poles
(b)
Figure 5.10: (a) Transfer function H(jω) magnitude and phase and b) coordinate of pole-zero of the
H(jω).
i(fs)
Cgd1
+
Vin1
-
gmVin1
Rds1
+
Vout
-
Z1(ω)
Z2(ω)
Cgs1
Cds1
Ld
Lg
Cgd2
Cgs2
Rds2
Cds2
gmVin2
Feedback
network
Figure 5.11: A basic two section DA, the main section is formed with Hartley Oscillator
configuration and the feedback network consists of multi-loops arrangement.
86
The following cases of the feedback network have been examined:
a) gm2 ≠ 0, Cgd2 ≠ 0, sweep either gm1 or Cgd2. The poles are unstable, and the pole evolution is shown in
Figure 5.12 (a) by sweeping gm2.
b) gm2 ≠ 0, Cgd2 = 0, sweep gm2. The poles are unstable, and the pole evolution is shown in Figure 5.12 (b)
by sweeping gm2.
c) gm2 = 0, Cgd2 = 0. The poles are stable.
d) gm2 = 0, Cgd2 ≠ 0, sweep Cgd2. The poles are stable.
(a)
(b)
Figure 5.12: Evolution of the poles in complex plane for case (a) and (b).
One should bear in my mind that to have unstable condition, it necessary that Z1(ω) and Z2(ω) must be
inductive while Cgd is present, and this is simply a Hartley Oscillator. Therefore, the gate and drain
transmission line can be investigated. For instance, review Figure 5.13 (a), where gate line (from
Figure 5.8) is redrawn. The imaginary part of Zin behaves as capacitive over a wide frequency range ,
refer to Figure 5.13 (b), and it is not possible to have an oscillation.
Lg/2
Zin
Lg/2
Rgt
Cgs
Real part
Impedance [Ω]
Rin
Imaginary part
frequency [GHz]
(a)
(b)
Figure 5.13: (a) Gate line transmission line (b) plot response of Zin imaginary part over wide
frequency range (in blue color curve). Note that real part is shown in red color curve where, it has
25 Ω at low frequency.
87
Let’s extend the analysis for the 2 section DA, as shown in Figure 5.14. The DA is analyzed with transient
condition and an initial voltage condition is introduced in the circuit. By selecting Cgd = 2.2 pF, Cgs = 5 pF,
Cds = 5 pF Lg = 10 nH, Ld = 10 nH, Rds = 200 Ω and gm = 100 mS. An odd mode oscillation is taking place
(mode +,-) at frequency of 600 MHz, and Q1 oscillates 180° out of phase with respect to Q2, and the
virtual ground in the middle, refer to voltage plot shown in Figure 5.15.
The symmetry of the DA topology facilitates the accomplishment of the oscillations conditions for odd
mode oscillations [192]. If the symmetry is not perfect the mode is not pure. The equivalent circuit of the
two section DA for odd mode oscillation can be simplified to Figure 5.16. The same oscillation condition
still can be obtained.
Initial voltage
given here
Rin
Lg/2
Ld/2
Q1
Cgd
Vg1
Vd1
+
Lg/2
Rdt
Cgs
gmVin
Rds
Cds
Ld/2
Vin
-
Virtual ground
Lg/2
Cgd
Vg2
+
Lg/2
Ld/2
Q2
Cgs
Vd2
gmVin
Rds
Vin
Cds
Ld/2
RL
Rgt
Vg2
voltage [V]
voltage [V]
Figure 5.14: Odd mode oscillation in two section DA, and virtual ground in the middle.
Vg1
Vd1
Vd2
time [ns]
time [ns]
(a)
(b)
Figure 5.15: Analysis plot of of active nodal i.e. Vg1, Vg2 , Vd1 and Vd2. The pink color curve for both
plots representing virtual ground of gate and drain line, respectively.
88
The gate and drain transmission line of Figure 5.16 is investigated. For simplicity, review Figure 5.17 (a),
where gate line is redrawn. The imaginary part of Zin behaves as inductance over a wide frequency range,
where Hartley Oscillation condition is fulfilled. The important point to be noticed is gate and drain
transmission line can be modified by inserting a positive real part element (compare Figure 5.13) to
improve stability condition to DA having more than single section
Rin
Rdt
Cgd
Lg/2
Ld/2
Vg1
Lg/2
Vd1
gmVgs
+
vgs
Cds
Cgs
Ld/2
Rds
-
Rin
Lg/2
Zin
Lg/2
Cgs
Impedance [Ω]
Figure 5.16: Equivalent circuit model of two section DPA for odd mode oscillation. The middle
reference plane is ground plane.
Real part
Imaginary part
frequency [GHz]
(a)
(b)
Figure 5.17: (a) Gate line transmission line (b) plot response of Zin imaginary part over wide
frequency range (in blue color curve). Note that real part is shown in red color curve where, it has
25 Ω at low frequency.
Analysis is extended to three section DA (as shown in Figure 5.18), different oscillation modes can
coexist [24], and they are depend on the initial conditionsFor example, mode (+,0,-) mode, where Q1
oscillates out of phase with Q3. The active node i.e. gate and drain point of the middle section behave as
virtual grounds, refer to the analysis plot shown in Figure 5.19 (a). On other hand, there is (+,-,+) mode is
discovered, where Q1 oscillates in phase with Q3, and out of phase with Q2. In practical, odd mode
oscillation is exists when the active device are combined in parallel configuration e.g. push pull or
balanced amplifier [146].
89
Initial voltage
given here
Rin
Lg/2
Q1
Cgd
Vg3
+
Lg/2
Rdt
Cgs
Ld/2
Vd3
gmVin
Vin
Rds Cds
Ld/2
-
Lg/2
Q2
Cgd
Vg3
+
Lg/2
Cgs
Ld/2
Vd3
gmVin
Vin
Rds Cds
Ld/2
-
Lg/2
Q3
Cgd
Vg3
+
Lg/2
Cgs
Ld/2
Vd3
gmVin
Vin
Rds Cds
Ld/2
Rgt
RL
Figure 5.18: Three section DPA arrangement to explain odd mode oscillation.
voltage [kV]
voltage [V]
Vg1
Vg2
Vg3
Vg1
Vg2 and Vg3
time [ns]
time [ns]
(a)
(b)
Figure 5.19: Analysis plot of of active nodal i.e. Vg1, Vg2 and Vg3. (a) shows odd mode oscillation
condition for (+,0,-) mode and (b) shows (+,-,+) mode.
90
5.4 Parametric oscillations detection in DAs
5.4.1
Introduction
The multi-section nature of DAs makes them prone to spurious oscillations due to presence of multiple
non-linear elements and feedback loops. In fact, under certain conditions, DAs can exhibit parametric
oscillations, i.e. spurious responses of autonomous nature that are a function of the input power or input
frequency. Several stability analyses based on small-signal S-parameter can be found in the literature for
DAs [158] - [159]. However, small-signal stability techniques are unable to detect parametric oscillations
and thus cannot guarantee circuit stability under large-signal regimes [165] – [166].
A procedure that includes both small-signal and large-signal stability analyses is used to firstly detect, and
secondly eliminate undesired oscillations, including those of parametric nature. The stability analysis is
based on determining the poles of a closed-loop transfer function resulting from linearizing the system
around a steady state regime [159]. The large signal stability results are used to understand the origin of
the instability in the DA and to determine optimum place and value of stabilization resistors that guarantee
sufficient stability margins with minimum degradation of its performance. The approach is illustrated
through the stabilization of a high-efficiency LDMOS DA (100 - 700 MHz). Original circuit exhibited a
parametric oscillation below 700 MHz deteriorating in-band performance. A second version of the DA with
the stabilization circuit has been successfully fabricated and has no stability problem is reported.
5.4.2
Stability Analysis of DA
Pole-zero identification of a linearized frequency response is again considered here for stability analysis
[162]. This technique has the benefit of being applicable to DC, small-signal and large-signal stability
analyses within a similar methodology and from simulations obtained in commercial CAD tools.
The stability verification of circuit under study begins with a small-signal stability analysis. The smallsignal current probe required to obtain the frequency response is introduced at the gate terminal of the
third section. Note that, except for exact pole-zero cancellations, the same stability information can be
extracted if the current source is injected at any other circuit node, as described in [162]. The resulting
pole-zero map is plotted in Figure 5.20 (a). Figure 5.20 (b) shows pole-zero map corresponding to the
small-signal stability analysis of the stabilized circuit. Since no poles with positive real part are present,
we can conclude that the circuit is stable under small-signal conditions. However, even though all poles
are stable, Figure 5.20 (a) shows the presence of a couple of conjugate poles with a very small absolute
value of their real part. This couple of critical poles is dangerously close to the right-half plane and reflects
the existence of a risky resonance about the frequency given by its imaginary part, about 760MHz. This
means that, although stable in small-signal regime, the circuit exhibits a low stability margin at that
frequency. Such high-frequency critical resonance is commonly found in DAs and has its origin in the
parasitic loop formed in the distributed structure through the gate drain capacitances of the FET devices
[161].
This resonance can become unstable if the gain of the individual section is increased as described in
[161], [163]. In order to ensure circuit stability under large-signal operation, it seems necessary to extend
the analysis, studying the evolution of these critical poles versus input power Pin. To this goal, a largesignal stability analysis is required. The small-signal current probe is maintained at the same node and
mixer-like harmonic-balance simulations, based on conversion matrix algorithm, are performed in order to
obtain the linearized frequency responses, as in [159], for each power level of the input drive Pin.
An input drive at 200MHz has been arbitrarily chosen for the analysis. The evolution of the real part of the
critical poles versus Pin is plotted in Figure 5.21, can be observed that for Pin > 11 dBm the poles have a
positive real part, indicating an unstable behavior that gives rise to a parametric oscillation. Eventually,
the circuit becomes stable again for Pin higher than 17.5 dBm. Analogous results are obtained for other
frequencies of the input drive.
The results obtained from this large-signal stability analysis confirm that the circuit, originally stable under
DC or small-signal regimes, exhibits an undesired parametric oscillation as the input drive increases. In
order to understand the origin of this instability, the evolution of the small-signal gain at 760MHz versus
the input drive (at 200 MHz) has been calculated with conversion matrix simulations. This is equivalent to
calculate the S21 at 760MHz in presence of a large signal at 200 MHz. Result is superimposed in
91
Figure 5.21 where a gain expansion phenomenon is clearly noticeable. This gain expansion is the
consequence of the deep class AB bias required by the circuit in order to achieve high efficiency. The
gain expansion at 760 MHz correlates with the evolution of the real part of the critical poles and it is
responsible for the undesired oscillation.
1.0
1.0
0.8
0.8
0.6
0.6
0.4
critical
poles
0.2
Im (GHz)
Im (GHz)
0.4
0.0
-0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
-1.0
-0.10
0.02
critical
poles
0.2
-0.08
Re (GHz)
-0.06
-0.04
-0.02
0.00
0.02
Re (GHz)
(a)
(b)
Figure 5.20: (a) pole-zero map (O zeros, X poles) corresponding to the small-signal stability
analysis of the original circuit. (b) pole-zero map (O zeros, X poles) corresponding to the smallsignal stability analysis of the stabilized circuit.
17
original circuit
stabilization resitor at 1st stage
stabilization resistor at 2nd stage
stabilization resistor at 3rd at stage
small-signal gain @760 MHz
16
15
14
0
Gain (dB)
Real part of critical poles (GHz)
0,02
13
12
-0,02
11
-10
-5
0
5
10
15
20
Input Power (dBm) at 200MHz
Figure 5.21: Evolution of the real part of critical poles versus Pin for the original circuit and the
three stabilization configurations, evolution of the small-signal gain @ 760MHz versus Pin and
frequency of input drive is 200MHz.
On the one hand, a frequency division by two is encountered for fin about 500 MHz and particular load
conditions and input drive levels. As an example, Figure 5.22 (a) shows a pole/zero map for
fin = 500 MHz, Pin = 17.1 dBm and ΓL = - 0.75. The presence of a couple of RHP complex conjugate poles
at fin/2 reveals the frequency division instability. Figure 5.22 (b) plots on the smith chart the values of load
termination ZL that imply frequency division for fin = 500 MHz, Pin = 17.1 dBm. The detected instabilities
have been experimentally verified through tuner measurements. The picture of the DA board is similar to
92
Im
the one given in Figure 5.25, but stabilization circuit is not included. As an example, Figure 5.23 shows a
measured frequency division by two is obtained for fin = 521 MHz, Pin = 16 dBm and ΓL = 0.75 ∠ 180º.
0.6
0.3
[Im]
0.0
-0.3
-0.6
-0.020
[Re]
0.000
× 2πe9
a)
b)
Figure 5.22: a) Pole/zero map showing the frequency division for fin = 500 MHz, Pin = 17.1 dBm and
ΓL = 0.75 ∠ 180º. b) Unstable (circles) and stable (crosses) values of ΓL for fin = 500 MHz and
Pin = 17.1 dBm.
40
Pout (dBm)
20
0
-20
-40
-60
0
100
200
300
400
f in (MHz)
500
600
Figure 5.23: Frequency division experimentally found in DA for fin = 521 MHz, Pin = 16 dBm and
ΓL = 0.75 ∠ 180º.
5.4.3
Circuit Stabilization and Measurement Results
As discussed in section 3.3, the design methodology i.e. from device selection, synthesizing gate/drain
line elements from device packaged values, until layout optimizations are applied in this section. The
basic design goal of the work is to achieve high efficiency for SDR driver PA applications, and the power
45
operation is ~27 dBm. Therefore, medium power device i.e. LDMOS device (RD01MUS1) is suitable.
The low DC supply operation is required for the device, which typically about 7.5 V. The drain loading
45
LDMOS n-type MOSFET packaged device from Mitsubishi (part number is RD01MUS1) is used.
93
effect of the device is not significant, but, however Xopt(ω) is important since it determines the drain line
cut-off frequency ωc. Copt of 8.2 pF is extracted by means of device modeling (with inclusion of packaged
properties). Therefore, effective drain line elements i.e. Li are synthesize according to (3.48), to form
desired ωc (~0.8 GHz). Dummy drain termination is eliminated to improve the efficiency performance
[106]. Simplified design schematic of 3-section LDMOS DA applying non-uniform drain line is shown in
Figure 5.17.
Ld3
Ld2
Ld1
Vdc
Cd2
Cd1
Q1
Impedance
transformer
Pout
Cd3
Q3
Q2
Rstab
Cga1
Pin
Lg1
Cga3
Cga2
Lg2
Lg3
Lm1
Lg4
Lm2
Cm1
Rgt
Cm2
Figure 5.24: Simplified design schematic of the high-efficiency LDMOS DA. The second version of
the circuit includes the stabilization resistor Rstab at second section of the DA.
m-derived section is implemented at both termination of gate line. Each device is fed with 5 V drain
supply voltage. Bias voltage of 2.1 V is applied to each gate resulting in class AB operation, with
quiescent current Idq of ~110 mA. Power performance due to load termination R for n = 3 is investigated.
The virtual impedance seen by the transistor in both directions depending on selection as illustrated in
section 4.2, and computed as given (4.16) - (4.23). A broadband impedance matching employing
low-pass LC elements are designed to transform impedance from 13 Ω to 50 Ω over the bandwidth of
100 – 700 MHz. The photograph of the high efficiency LDMOS DPA is shown in Figure 5.25. The size
area of the board is 27 mm × 13 mm.
To find the best compromise between stability and circuit performance it is essential to combine the largesignal stability analysis with a judicious stabilization strategy. The parametric oscillation being associated
to a gain increase, circuit stability should be improved by introducing series resistors at the gate of any of
the three transistors. Since the inclusion of series resistors will impact circuit performances, an evaluation
to obtain the better place and value is needed. Three stabilization configurations are here compared.
Each case corresponds to the inclusion of a unique 5 Ω series resistor at the gate of one of the
transistors. The evolution of the critical poles versus Pin (with fin = 200 MHz) for the three cases is plotted
in Figure 5.21. As deduced from Figure 5.21, any of the three possibilities is sufficient to maintain the real
part of the critical poles at negative values. However, the best stability margin is obtained placing the
series resistor at the second section, while the lowest is achieved when the series resistor is located at
the first section.
PAE is the goal performance in this design, the simulated PAE (at Pin = 19 dBm) for the three
configurations is shown in Figure 5.26, where they are compared to the original design. Results show that
placing the resistor at second or third section has low impact on PAE. However, the resistor located at the
first section offers the strongest degradation of PAE, especially at high frequency. Therefore, the location
of the series resistor at the second section was eventually selected since it provides the best stability
margin with low PAE degradation. Once the choice is made and before circuit fabrication, an exhaustive
stability analysis (varying load and input drive) of the circuit with the series resistor connected at the
second section is performed. This analysis serves to confirm circuit stability for any power and frequency
94
of the input drive and for any circuit load. As an example, results of the small-signal stability analysis for
the circuit with the stabilization resistor are shown in Figure 5.20. It can be observed how stability margin
has been increased compared to original circuit (critical poles shifted leftwards).
Vdrain
GND
27 mm
13 mm
Impedance
transformer
LDMOS
device
RFout
Vg1 Vg2 Vg3
RFin
Figure 5.25: The photograph of the high efficiency LDMOS DA. The size of the board is
27 mm × 13 mm.
The 3-section LDMOS DPA with stabilization resistor in the second section has been fabricated and
characterized. Note that same board as shown in Figure 5.25 is used but the series resistor at gate Rstab
of the second section is inserted. Measured PAE and gain results are superimposed in Figure 5.26. The
rest of measured performances include Pout ~30 dBm and gain of 10 dB over the frequency range of
interest (100-700 MHz). Contrarily to original circuit, no parametric oscillations are reported at any
frequency and input drive. Figure 5.27 show example of measured spectra at 700 MHz, indicating there is
no oscillation is reported in measured level.
50
PAE(%)
40
30
20
10
100
original circuit (simulated)
stabilization resistor at 1st stage (simulated)
stabilization resistor at 2nd stage (simulated)
stabilization resistor at 3rd stage (simulated)
measurements of stabilized circuit
200
300
400
500
600
700
Frequency (MHz)
Figure 5.26: PAE simulation results of original circuit and the three stabilization configurations for
Pin = 19 dBm. PAE measurement results of stabilized amplifier for Pin = 19 dBm.
95
40
700 MHz
20
P o u t [d B m ]
0
-20
-40
-60
-80
-100
70 MHz
Frequency [MHz]
900 MHz
Figure 5.27: Example of measured of power spectra at 700 MHz, and there is no oscillation is
reported.
5.5 Conclusion
The basic principle of stability analysis with the intent of understanding the strategies is discussed. For a
first time, pole-zero identification technique is applied to the DA, to understand the origin of the oscillation
nature due to the multi-loops nature. The analysis considers the DA as a basic feedback oscillator circuit
i.e. Hartley Oscillator and using a simplified transistor model. The origin of the DA oscillation can be
pointed to the trans-conductance nature or multi-loops nature associated due to the feedback network. An
explanation of odd mode oscillation in DA topology is investigated, which is useful for practical
applications.
Large-signal stability analysis based on pole-zero identification is applied to analyze parametric
oscillations in high-efficiency DA. The parametric oscillation is correlated to a gain expansion
phenomenon that directly affects the critical poles of the circuit. Therefore, design of larger small-signal
stability margins is required since those margins may decrease under large-signal conditions.
Large-signal stability analysis is then used to stabilize a high-efficiency 3-section LDMOS DA with a
minimum impact on circuit performance.
96
Chapter 6.
Distributed Power Amplifiers for SDR Applications
A Distributed Power Amplifier (DPA) is simply a DA which high power FETs are used instead of the
small-signal FET devices [103]. DA has already demonstrated high performance for small-signal
broadband operation, but has limitation of output power performance [5]. They represent attractive
candidate for high power SDR application [14] – [15]. Each transistor demonstrates a strongly frequency
dependent power behavior so that the overall output power is only a small fraction of the combined power
capabilities for all active devices [80], [102]. The limitation to achieve high output power with DPA can be
addressed on both the device technology and circuit design [167], [16]. The realization of DPA has posed
a significant challenge due to the electrical and thermal limitations of GaAs or HBT transistor technology
[16]. In recent years, AlGaN/GaN technology has established itself as a strong contender for such
applications, because of its large electron velocity, bandgap, breakdown voltage Vbk for current-gain
cut-off frequency fτ , and sheet carrier concentration [16]. Few recent DPA circuit design techniques i.e.
drain impedance tapering [11], [12], [91], [83], [115], non-uniform device periphery [103], cascode [168],
[104], cascaded non-identical transistors [14], [13], [169], dual-fed [23], [170] and extended resonance
power combining [172] lead to high output power performance over bandwidth frequency operation.
This chapter discusses on the DPA development for Software Defined Radios (SDR) applications. The
first DPA development demonstrated output power of 10 W and gain of 32 dB, covering 40-2000 MHz,
and PAE >15% employing single section cascaded non-identical high-fτ transistors and power transistor,
and with implementation of an inter-stage tapered impedance [14]. The second DPA development is
discussed on vectorally combined DPA with load impedance determination, has demonstrated optimum
power and PAE performance i.e. ~23 W and >35%, respectively with gain of 36 dB over frequency from
40-2000 MHz [15], [13]. Transformer/filter by means of RFT is designed from 12 Ω to 50 Ω, and excellent
insertion loss of 1.1 ± 0.9 dB is recorded experimentally over the 40-2200 MHz frequency range
[26] - [27].
6.1 First DPA development
6.1.1
Motivation
Several gain stage configurations that are widely used in DA as shown in Figure 6.1 (a) - (d), [14], [169],
[171]. Figure 6.1 (a) is a common source type, it provides a decent gain and very large bandwidth.
Figure 6.1 (b) is a cascode structure used to enhance reverse isolation, and this structure does not
provide higher trans-conductance gm than common source transistor, and thus does not have
considerable gain advantage over that in Figure 6.1 (a). Figure 6.1 (c) shows the cascade common
source gain structure, where two identical transistors are connected with each other through peaking
inductor and a series resistor [169]. In Figure 6.1 (d), proposed topology of cascaded two non-identical
transistors with inter-stage tapered impedance [14].
The motivation of this section is to design high power (10 W) and high gain DPA for SDR PA applications,
and the operating bandwidth up to 2 GHz. Due to loading effect of the bigger size transistor, DC-RF
energy conversion is not optimum as the frequency increases towards cut-off frequency. These
amplifiers, in fact, have never exhibited high power and high gain performance simultaneously. Beyer et
al. have showed that gain in conventional DA cannot be increased indefinitely by adding more sections
[4]. However, few works have shown high output power with DA topology while preserving reasonable
gain [11], [12], [104], [168]. The work by [14] demonstrated best performance in output power-gain
response within an operating bandwidth up to 2 GHz. The comparison of these works are summarized in
Table 6.1.
Achieving high output power with DA is very challenging. Conventional DA design is different to reactively
matched design because the drain line is fixed to approximately 25 Ω with constant-k ladder [173], and
97
could be higher value if the drain line is tapered. RF current swing is the main limitation to power increase
due to the high impedance of the tapered drain line [11]. To increase power the device gate periphery
must be increased, but input capacitance Cgs increases as well. A capacitively coupled technique [35]
allows power handling increase with constant bandwidth and gain. However, this technique never
demonstrated high gain and high output power simultaneously.
Vout
Vout
Vgate
Vin
Vin
(a)
(b)
Vout
Vout
R
jX
L
G
Vin
jB
L
Vin
(c)
(d)
Figure 6.1: Several gain stage configuration used in DA (a) common source (b) cascode [171]
(c) cascaded two identical transistors common source gain [174] (d) cascaded non-identical
transistors and inter-stage tapered impedance [14].
This work
[14]
Zhao et al.
[11]
Gassmann et al.
[12]
Xie et al.
[104]
Fraysse et al.
[168]
Lin et al.
[175]
Power
>38 dBm
>35 dBm
>37 dBm
>39 dBm
34 dBm
>37 dBm
Gain
32 dB
9 dB
7 dB
12 dB
9 dB
11 dB
PAE
>15%
>20%
30-70%
30-70%
>20%
>27%
BW
0.04-2 GHz
0.1-2 GHz
2-15 GHz
0.02-2 GHz
2-8 GHz
0.02-3 GHz
Num.
section
1
5
5
4
6
3
Fabricated
Hybrid
Hybrid
MMIC
Hybrid
MMIC
hybrid
Device
pHEMT +
GaN HEMT
LDMOS
GaN HEMT
GaN HEMT
HBT
GaN HEMT
Table 6.1: Comparison of high power-gain response DPA works
Many techniques have been reported to improve gate line matching problem in DA such as tapering of
device gate-widths [113], tapering the capacitors connected in series with transistor inputs [176], and
tapered gate line for gaining equal voltages at the transistors by moving characteristic impedance higher
98
than 50 Ω [103] and tapering the gate line to reduce gate line mismatching [173]. Image impedance of the
constant-k filter causes gain peaking (expansion) close to cut-off frequency ωc. The first attempt to
achieve wideband matching solution using non-identical high-fτ transistors in cascaded DPA is discussed
in [169], where an adjustable inter-stage matching network between the two non-identical high-fτ
transistors is introduced.
In this work, a broadband match to the input gate of the power transistor to achieve high output power
and high gain is discussed simultaneously [14]. The controlled inter-stage tapered impedance provides
wideband matching solution between two non-identical transistors 46 (high-fτ and power transistor) while
reducing the peaking effect and stability margin is guaranteed. Stability verification of the topology based
on pole-zero identification [162] is performed.
6.1.2
Circuit Analysis
Constant-k network isolates the parasitic capacitances of the transistors to form wide bandwidth response
with lumped inductance. This frequency dependent impedance implies that fixed impedance (e.g. 50 Ω
termination) cannot provide ideal matching transformation. A constant real termination causes ripples as
the signal moves towards cut-off frequency due to unmatched power that reflects back to the input since
the imaginary has not been cancelled [173]. It is worthwhile to trade-off the low frequency matching to
improve matching at high frequencies.
A high-fτ transistor (typically has lower input parasitic capacitance Cgs and break down voltage Vbk, e.g.
SiGe, HBT or pHEMT device is coupled to the input of the power transistor (i.e. GaN HEMT device) with
tapered impedance termination ZT, as shown in Figure 6.2. ZT improves matching near cut-off frequency
ωc with minimum trading-off at low frequency. Typically output capacitance C’ds of the high-fτ transistor is
much lower than C’’gs of the power transistor. In this work we make assumption C’’gs ≈2⋅C’ds, however the
concept is applicable to any ratio of C’’gs/C’ds. Figure 6.3 shows general configuration of two non-identical
transistors (high-fτ transistor and power transistor) terminated with inter-stage tapered impedance
matching. The impedance Zin seen by the current source ii is illustrated in Figure 6.4. The ZT could be
proposed with any suitable broadband inter-stage impedance termination. In this work, a proposal of ZT
which is consists of three elements i.e. jX, jB and G is used, as shown in Figure 6.5.
To begin the explanation of the concept technique (as shown in Figure 6.4), the impedance Zin seen by
the current source ii will be analyzed. Figure 6.5 which is simplified schematic of Figure 6.4 will be used.
The analysis will focus on achieving optimum matching up to ωc in order to overcome reflection (poor
matching) caused by constant-k network near ωc. Vgs has proportional behavior to Zint. The impedance Zint
is given by
Z int =
4 − 4 XB − 2ωLB + j 2(ωGL + 2GX )
,
4G − 2ωGXC − ω 2GLC + j (2ωC + 4 B − 2ωXCB − ω 2 LCB)
(6.1)
where L and C values will determine the cut-off frequency ωc of the line. From Figure 6.5, C/2 is referred
to C’’gs. The elements e.g. G, X and B are shown in Figure 6.1 (d).
46
The motivation to use non-identical transistors is to maximize DC-RF conversion at each transistor stage while achieving high
gain operation over the frequency bandwidth range. However, to achieve wideband matching between two different non-identical
transistors with conventional method is difficult to achieve.
99
L
High-fτ
transistor
Gate line
ZT
Drain line
Power
transistor
Figure 6.2: Schematic of cascaded distributed power amplifier with non-identical transistors and
controlled inter-stage tapered impedance for wideband solution.
Drain line
ZT
Rgt
Ld
0.5Lg
Lg
C’’gs
C’gs
C’’ds
Rdt
C’ds
ii
0.5Ld
Inter-stage match with
ZT
Gate line
Figure 6.3: Configuration of 2-stage non-identical transistor where the first is high-fτ and second
transistor is power transistor, inclusion of an inter-stage matching configuration with tapered
termination.
Zint
+
vin
-
L1
L2
+
ii
C’ds
output of high-fτ
transistor
vgs
C’’gs
ZT
input of power
transistor
Figure 6.4: Schematic to illustrate the impedance Zin which seen by the current source ii.
100
L/2
Zint
ZT
jX
ii
+
vgs
C/2
jB
G
-
Figure 6.5: Simplified of Figure 6.4 to give explanation of Zint, and ZT is consists of three elements
i.e. jX, jB and G.
Zint real and imaginary parts at ωc are analyzed as a function of jX and jB. A numerical example is given
for illustration purposes, L = 6.93 nH and C = 2.77 pF are selected, providing ωc = 2.3 GHz. The careful
selection of G is required to minimize by variation of Zint real over entire bandwidth response. The
improved match at ωc (68 Ω real part and zero imaginary) requires B = 0.02076 and X = 10 (for case
G = 0.018), as shown in Figure 6.6. For same value of B = 0.02076 (while fixed G) to keep the Zint
imaginary null, various value of X can be chosen. However, to lead to an optimum design across the
bandwidth, Zint real at ωc must be as closer to low frequency. Therefore, by selecting an appropriate
termination at any frequency, the matching can be improved. As a result, the inter-stage termination
impedance is tapered.
The plot in Figure 6.7 shows the frequency response of the impedance Zint. As for comparison, the fixed
termination impedance (50 Ω) is included in the plot. From the plot, the real part of Zint is almost constant,
e.g. almost 55 Ω over the entire bandwidth and the imaginary part is null. As for the conventional
approach (fixed termination), strong peaking in real part is observed close as frequency reaches close to
ωc and the imaginary part deviates to capacitance. From Figure 6.5, Vgs will have proportional behavior to
Zint.
When B=0.02076, for
various case of X, different
real part can be chosen
X=10
Imaginary part is
null for various
case of X
X=10
X=1
X=5
X=2
X=1
(a)
(b)
Figure 6.6: The real (a) and imaginary (b) part of Zint evaluated at cut-off frequency versus B
(susceptance) for few cases of X (for fixed G of 0.018).
101
300
real (tapered)
imaginary (tapered)
200
Impedance [ohm]
real (fixed)
imaginary (fixed)
100
0
-100
ωc = 2.3 GHz
-200
0
0.5
1
1.5
2
2.5
3
Freq [GHz]
Figure 6.7: Zint real and imaginary parts with tapered impedance (red line) and fixed termination
(blue line).
To extend the explanation of the concept for any ratio of C’’gs/C’ds, Figure 6.8 is used. In practical
application, Cgs’’ of the power transistor could be more than 2 times of Cds’ of the high-fτ transistor. Cgs’’ is
approximately 2.4 times of the C’ds for gate periphery ratio of 8 times [169]. To deliver maximum power
from the current source ii the impedance Zint must have zero imaginary part and gain peaking must be
minima for stability considerations. In conventional method (fixed termination) the imaginary part behaves
at capacitive region near ωc. Zint seen by the current source ii due to any ratio of C’’gs/C’ds is given as
Z i nt
2Z T
j 3ωL
− 2ω 2 LZ T +
− jω 3 L2
mC 'ds
mC 'ds
.
=
2
3ω 2 L
j 2ωZ T
2
4 2
3
−ω L −
+ ω L C 'ds +
+ j 2ωZ T − j 2ω LC 'ds Z T
mC 'ds
m
m
(6.2)
The benefit of the proposed ZT network is significant when the m ratio increases. For instance, let
consider m = 2.4. Again, a numerical example is given for illustration purposes, L = 6.93 nH and
C = 2.77 pF are selected, providing ωc = 2.3 GHz. Negative value of X and lower value G are needed to
improve match at ωc. The improved match at ωc (85 Ω real part and zero imaginary) requires B = 0.05227
and X = -3 (for case G = 0.012), as shown in Figure 6.9. A careful selection of G is necessary to provide
required real part Zin across the bandwidth and keep the real part Zint with minimum variation. Since the
G = 0.012 (or equals to 83 Ω) and at ωc, the real part Zint is approximately 85 Ω (with zero imaginary part).
The X (of negative value) would be absorbed to the line inductance L/2. However, suitable values of G, jX
and jB depending on the design need for any ratio of m can be easily obtained through the numerical
analysis.
As discussed in Chapter 3, gain in common source DA cannot be increased indefinitely by adding more
sections due to losses of the lines [4], and the increase in number of section will directly impact the cost
and implementation of size area. Trans-conductance gm of each section device is the most important
issue for the gain. Figure 6.10 shows a small-signal equivalent circuit of the proposed circuitry to
determine gm (from Figure 6.3). The analysis will lead to determine the overall trans-conductance gm due
to high-fτ and power transistors gm1 and gm2, respectively, and the influence of the ZT especially over the
entire bandwidth frequency.
102
Zint
ZT
L
L/2
jX
+
vin
-
C’ds
ii
output of high-fτ
transistor
+
vgs
C’’gs
-
tapered
impedance
termination
jB
G
input of power
transistor
Figure 6.8: Schematic to illustrate the impedance Zint is seen by the current source ii.
Corresponding to B=0.05227,
and X=-3, real part Zint
X=-3
equals 85 Ω
Imaginary part is null
for various case of X
X=-3
X=-4
X=-5
X=-4
X=-7
X=-5
X=-7
Figure 6.9: The real (a) and imaginary (b) part of Zint for circuit shown in Figure 4.8 for m = 2.4,
evaluated at ωc versus B (susceptance) for few cases of X (for fixed G of 0.012).
gm is defined as change of drain current ID with respect to the corresponding change of gate voltage VGS
with drain supply voltage VDS equals to constant [177],
g m = ∂I D / ∂VGS .
(6.3)
The voltage across the input capacitor of the power transistor vgs2 with inclusion of inter-stage tapered
impedance ZT is as the following,
vgs 2 = 1 / jωC ' ' gs //( jω L / 2 + ZT ) ⋅ iL ,
where Z T =
(6.4)
1
+ jX and iL is the current that flowing across L.
G + jB
Substituting iin = gm1vin into (6.4),
103
iL =
1 / jωC 'ds
⋅ g m1vin ,
1 / jωC 'ds + jωL + [1 / jωC ' ' gs //( jωL / 2 + ZT )]
(6.5)
and thus
v gs 2 = g m1vin
1 / jωC 'ds ⋅[1 / jωC ' ' gs //( jωL / 2 + Z T )]
1 / jωC 'ds + jωL + [1 / jωC ' ' gs //( jωL / 2 + Z T )]
.
(6.6)
ZT
jX
jB
R
L/2
Vin
Vout
gm1
+
vgs1
-
L
iin
C’gs
C’ds
+
vgs2
-
high-fτ transistor
gm2
iout
C’’gs
power transistor
Figure 6.10: Small signal model for gain analysis including two non-identical transistors with
inter-stage tapered impedance.
Therefore, one can derive gm for the circuit shown in Figure 6.10,
gm =
∂io ut g m 2 vgs 2
,
=
vin
∂vin
(6.7)
where gm1 and gm2 are intrinsic trans-conductance of the respective transistors. By substituting (6.6) into
(6.7), one can derive
g m = g m1 g m 2
1 / jωC 'ds ⋅[1 / jωC ' ' gs //( jωL / 2 + Z T )]
1 / jωC 'ds + jωL + [1 / jωC ' ' gs //( jωL / 2 + Z T )]
The simplification of (6.8) by substituting jω → s
47
47
.
(6.8)
, thus one can show gm as
Laplace transformation F(s), where s = σ + jω, of a continuous function f(ω) over the entire time domain(ω = 2π/t) is defined as
α
F ( s ) = ∫ f (t )e − st dt [109].
−α
104
g m = g m1 g m 2
1 / sC 'ds ⋅[1 / sC ' ' gs //( sL / 2 + ZT )]
1 / sC 'ds + sL + / sC ' ' gs //( sL / 2 + ZT )
.
(6.9)
Normalization of the trans-conductance G(s) can be written as
gm
= G ( s) ,
g m1 g m 2
(6.10)
and can be written as
G( s) =
s mL (C 'ds ) + s mL(C 'ds )
4
2
2
3
2
sL + 2ZT
,
ZT + s (mLC 'ds +3LC 'ds ) + s(mC 'ds ZT + 2C 'ds ZT ) + 2
2
(6.11)
where m = C’’gs/C’ds.
G(s) is analyzed for few cases of m (2, 2.4, and 3), when L = 6.925 nH, C’ds = 1.385 pF chosen to define
ωc = 2.2 GHz, and ZT is fixed termination, e.g. 50 Ω. The transfer function of G(s) as given in (6.11) is
identified using Scilab program. As shown in Figure 6.12, when ZT = 50 Ω is selected, 1 zero (only real
part) and 4 poles (which are in complex conjugate location) exist, and all lie on the Left Half Plane (LHP)
and have positive real functions. The zero for any case of m does not change. The two complex
conjugate poles which are located on close to the complex imaginary axis of left s-plane boost up the
G(s) at ωc. However, as m increases, the complex conjugate poles move lower to x-axis, and reducing the
bandwidth operation. This is clear evidence that with fixed termination ZT, bandwidth operation reduces
as m increases. The roots (zero and pole) are illustrated in Figure 6.13 (a).
With the proposed design technique, ZT helps to remain bandwidth operation as m increases. ZT can be
defined as
ZT =
1 + sGLx + s 2 BLx
,
G + sBx
(6.12)
where jωLx = jX and jωBx = jB from (6.4). It has been explained previously that for any m case, ZT
elements (e.g. G, B and X) are determined numerically from (6.2).
By substituting (6.12) into (6.11), and knowing ZT elements for any case of m, the roots of G(s) are plotted
in Figure 6.11 (b). The complex conjugate pole at imaginary axis is located at higher frequency with ZT
compared to fixed termination. It is evident from theoretical point of view that the tapered impedance
significantly improved bandwidth performance compared with fixed termination. In similar manner, G(s)
from (6.11) can be analyzed in ω domain by means of Inversion Laplace transformation 48 . The plot is not
shown in this section, but, however is given in Figure 6.16, inclusion of the device and passive models
are included in the analysis. Clearly, the bandwidth operation is extended significantly with new concept
technique.
48
Inversion Laplace f(t) of a continuous function F(s) can be found in [109], where the complex variable s = σ + jω,
f (t ) =
1 σ 1 + jω
F ( s )e st ds .
2πj ∫σ 1 − jω
105
Im
Im
15
m=2
4e5
m=2
m = 2.4
m = 2.4
m=3
m=3
2000
10
5
-1.4e10
-4
100
Re
Re
-2
-1.4e
10
-7e5
-200 -100
-100
-5
-10
-200
-15
-4e5
(a)
(b)
Figure 6.11: Roots of G(s) for (a) fixed termination (ZT = 50 Ω) and (b) tapered termination for few
cases of m.
6.1.3
Stability Analysis
Gate and drain line terminations must be provided for gain flatness reason as well as for stability
consideration [11], [91]. Series gate resistors were used at gate of lower FET DPA to improve the stability
[163]. However, due to implementation of the line terminations and the series resistors, PAE and gain will
degrade. The parametric oscillation issue due to gain expansion (peaking effect) in DPA is explained in
[25]. The advantage of inter-stage tapered impedance matching between the non-identical transistors
reduces the gain peaking effect near cut-off frequency [14] and does not required additional stabilization
circuit which may reduce circuit performance.
In order to verify the stability of the topology concept, the technique based on pole-zero identification to a
frequency response that represents the system linearization about a steady state is used [157]. The polezero identification technique can be applied either to a linearization about the DC bias point or to the
system linearized about a large-signal steady-state driven by the input signal [158]. For the latter,
conversion matrix simulation is used to obtain the linearized system frequency response [160].
A small-signal current probe in is introduced at the gate of the power transistor, as shown in Figure 6.12.
Sweeping the frequency fp of the probe (from fpmin to fpmax) and computing the voltage vn at the insertion
node allows determining the impedance seen by the probe Zp. It has been discussed in Chapter 5 that Zp
has negligible affect due to different active nodal selections of the current probe injection. The obtained
frequency response Zp and the corresponding pole-zero diagram are plotted in Figure 6.13.
The circuit is stable since all poles lye on the left-half plane. A dominant pole associated to the gain
peaking at the ωc (called “critical pole”) appears at 1.9 GHz. The resonance associated to this critical pole
106
is mild which translates into a large stability `margin (the critical pole is sufficiently far from the imaginary
axe). However this critical resonance can be strongly affected by the mismatch created by a change in
the load termination. A stability analysis is repeated using a fully reflective load with varying phase (from
0º to 360º), since this represents a worst case in terms of mismatch. The evolution of the critical pole is
superimposed in Figure 6.13 (b) in diamonds. As phase of load termination varies, the poles evolve in the
complex plane but remain inside the left-half plane for every phase value, thus guaranteeing circuit
stability under any load conditions. This confirms in this analysis that the obtained stability margin is
enough to account for pole-shifts due to changes in load termination.
current perturbation in
fp:fpmin↔fpmax
vn
Zp
inter-stage
tapered
impedance
inter-stage
tapered
impedance
high-fτ
transistor
Drain line
power
transistor
Gate line
Hcln(jωp)=vn(jωp)/in(jωp)
Figure 6.12: A perturbation current in is injected at active nodal of gate power transistor. Current
probe impedance seen Zp can be obtained by dividing vn/in.
2
40
m ag (Z p )
20
dB
1,8
Im(GHz)
0
100
deg .
p h a se ( Z p )
0
1,6
critica l p o le
1,4
1,2
-100
0.0
0.5
1.0
1.5
2.0
2.5
freq ( G H z )
(a)
1
-0,8
Re(GHz)
0
(b)
Figure 6.13 (a) Magnitude and phase of closed-loop frequency response Zp with 50 Ω load
termination (b) Associated pole-zero map (for simplicity only the positive imaginary part of the
complex plane is plotted). Black triangles: poles for 50 Ω load termination; circles: zeroes for 50 Ω
load termination; diamonds: evolution of critical pole versus the phase of a fully reflective load.
107
6.1.4
Design and Measurement Prototype
A. Objective
The objective of this work is to achieve high power and high gain covering bandwidth operation of
40-2000 MHz, so that the DPA system can be coupled directly to VCO. The VCO output is typically
~8 dBm, and the output power of 10 W is the design goal over the entire bandwidth operation
(40 - 2000 MHz). Thus, gain of 32 dB is required to deliver output power of 10 W. As an additional, the
amplifier must be stable under any load termination variation. Refer to Table 6.2 for the design goal
requirement of first DPA development for SDR applications.
B. Design Example and Layout Considerations
As discussed in section 3.3, the design methodology i.e. from device selection, synthesizing gate/drain
line elements from device packaged values, until full-wave simulation/layout optimizations are applied in
this section. Break-down voltage Vbk of the GaN device is ~73 V, which is close to the computation value
from (3.34). The drain loading effect of the device is very significant. Ropt(ω) of the high-fτ transistors are
not significant when it loaded in the output drain line. Since the GaN device will be loaded with Ropt(ω), the
output drain current generated from the device is not fully contributed to the load termination. To present
the output device with 50 Ω image impedance (without any matching transformation), one can perform
load pull determination of the device, ~10 W is promising up to 2 GHz with 28 V DC supply voltage. Take
note that the input impedance is terminated with 25 Ω due to the fact that half arm of 50 Ω constant-k
image impedance will be matched. However, the critical design part is to couple non-identical high-fτ
transistors to the GaN device with wideband matching technique, to achieve high gain solution.
As a test vehicle of the design approach, the achievement of high power and high gain in the
10-2000 MHz operating range is attempted, allowing the resulting DPA to be coupled directly to the VCO.
Two non-identical high-fτ pHEMT transistors with gatewidth of 800 μm and 6400 μm, respectively from
49
50
Avago Inc. are cascaded to the power transistor (GaN device from CREE Inc. having gatewidth of
3.6 mm) with inter-stage tapered impedance, where each transistor is featured by high gate periphery
ratio to achieve high power-bandwidth products.
Parameter
Bandwidth
Output power
Gain
Stability
Goal
40 MHz - 2000 MHz
10 W
32 dB
No oscillation
Table 6.2: Design goal requirement of the first DPA development.
Effective input/output real and imaginary part of the packaged devices (high-fτ and power transistors) are
extracted, as discussed in section 3.3. Input and output reactance (imaginary part) of the devices Xin(ω)
and Xopt(ω) 51 , respectively are tabulated in Table 3.1. For instance, Xopt(ω) of the second output high-fτ
transistor will be matched to the Xin(ω) of the input power transistor (GaN device) by means of theoretical
approach presented in section 6.1.2.
One should take note that phase synchronization is not necessary for the cascaded DA topology [129],
but the effective input capacitance Cin of the first high-fτ transistor and effective output capacitance Copt of
the power transistor are important to form ωc. As shown in Table 3.4, the effective Cin of the first high-fτ
transistor and Copt of the power transistor are lower than 3 pF, which means ωc of 2.2 GHz can be formed
49
The manufacturer part number of the high-fτ transistors are ATF511P8, and ATF54143, respectively from Avago Inc., San Jose.
The manufacturer part number of the power transistor is CGH40010F, from CREE Inc., North Carolina, US.
51
Zin(ω) and Zopt(ω) of each device are extracted as summarized in Table 3.1.
50
108
with 50 Ω load, according to (3.6). Therefore as shown in section 3.3, effective gate and drain line
elements i.e. Li are synthesize by means of (3.48) to form desired ωc. Dummy drain termination is
eliminated to improve the efficiency performance [16]. The elements of ZT1 and ZT2 have different value,
since it provides wideband matching solution between the respective inter-stage networks. Simplified
design schematic of the DPA topology is shown in Figure 6.14.
DC bias networks including gate and drain feeding for each transistor are illustrated in Figure 6.14. As
explained in section 3.3, Lg-Cg and Ld-Cd network (from Figure 3.20) are implemented. As the next step,
integration the DC bias network to the DPA topology is necessary while satisfying the RF to DC isolation
52
over the wide bandwidth response. For the first and second high-fτ transistors, Ld and Cd of 180 nH and
53
33 pF , respectively are selected for bandwidth operation up to 2 GHz [11]. For the final stage, the DC
feeding line is connected to high Q air-wound coil 54 .
Vd2
Vd1
Vg2
Vg3
ZT1
ZT2
nd
2 high-fτ
transistor
st
1 high-fτ
transistor
Pout
Power
transistor
Pin
Rgt
Vd3
Rdt
Vg1
Figure 6.14: Simplified schematic of the DPA; high-fτ transistors cascaded to the power transistor
with inter-stage tapered impedance. The gate and drain line are formed with constant-k ladder
network for 50 Ω input and output impedances.
To verify the design example, simulation with Harmonic Balance (HB) 55 is carried out to understand its
56
power performance. The non-linear models of the devices, and passive elements model
were
developed by Modelithics Inc. For comparison purpose, simulation template with inter-stage fixed
termination impedance is developed. The simulated results of drain voltage of each device, and power
performance are shown in Figure 6.15 and Figure 6.16, respectively. It is clear that the performance with
inter-stage tapered termination is significantly improved compared to the fixed termination. The drain
voltage of each transistor is kept constant over the entire bandwidth operation, as shown in Figure 6.15.
For tapered termination, output power and gain of 40 dBm and 32 dB, respectively achieved a flat
response up to 2.2 GHz (refer to Figure 6.16). It is an evident that bandwidth with new topology is
extended by 500 MHz compared to the fixed termination.
52
The high-Q ceramic 0603HP series chip inductors provided by Coilcraft Inc., and the Q up to ~150 at 1.7 GHz.
This is broadband high-Q capacitor 3060 size from Murata Inc, and details can be obtained at www.murata.com.
54
The inductance value of the air-wound coil is approximate to 43.5 nH, from Taito Yuden Inc.
55
The first attempt of the simulation excluded layout structure considerations, but the final simulation is optimized with ADS
Co-Simulation (CST) assisted with HB.
56
All the device and passive models are developed by Modelithics Inc., except for the GaN device model is performed at ITHE,
RWTH Aachen.
53
109
Drain Voltage [V]
power transistor
2nd high-ft transistor
1st high-ft transistor
Frequency [GHz]
Figure 6.15: Simulation results of drain voltage of each non-identical transistors for inter-stage
tapered (straight line with circle) and fixed termination impedance (straight line only).
Power [dBm], Gain [dB], PAE [%]
Bandwidth extension by ~500 MHz
Power
Gain
PAE
Frequency [GHz]
Figure 6.16: Simulation results of power performance i.e power, gain and PAE of cascaded DPA
with inter-stage tapered (straight line with circle) and fixed termination impedance (straight line
only).
In order to experimentally validate the concept technique, a prototype board of the design is using Rogers
4350/4450B PCB (printed circuit board) material is used. The DC biasing terminals are bypassed to
57
ground with multiple chip capacitors (e.g. 100 pF, 33 nF, 10 uF, etc) , refer to Figure 6.18. For the gate
57
The capacitors are referring to 600S Series Ultra-Low ESR, high Q microwave capacitors, from ATC Inc. Other capacitors are the
series is 545-L Ultra-broadband high Q capacitors, from Murata Inc.
110
biasing, high Q chip inductors (value of 220 nH, same series from Coilcraft Inc.) are used. A series
resistor of 3 Ω is included in the biasing circuitry as a precaution of oscillation in measurement level.
58
4-layers high density Rogers PCB and the bottom layer are connected with grounded heat-sink, and the
detail of the layer structure is in Figure 6.17. The components placement takes place at top of Layer 1.
Layer 2 provides grounding for quasi-TEM transmission line e.g. microstrip and Layer 4 is solid bottom
ground. Via-hole will be connecting from top layer to the bottom layer. Open grounding area with
adequate via-hole, and DC and RF routing are well isolated in PCB for minimum spurious. If an additional
DC routing is required, then possible to implement at Layer 3. However, no additional DC routing is
needed for this design. Modeling with full-wave EM simulator including PCB layers stack-up, via holes,
indium foil, grounded heat-sink, and RF connectors modeling [21] are considered. For GaN power
59
transistor, grounded heat-sink is attached at bottom layer via the indium foil and multiple screws, is
shown in Figure 3.22. To understand the grounding behavior of the GaN device, the contact between the
screw thread and the heat-sink is investigated in that EM simulator, and an important point to be noted is
the contact between the screw thread and heat-sink influenced the grounding of the device, especially at
higher frequencies. One way to improve the grounding is to use bigger diameter and more number of
screws to trade-off with the surface contact of the screws.
The layout from Cadence (ODB++ file) is imported to the CST. Discrete ports for the component pads are
created, and the layout information is exported to the ADS. ADS Co-Simulation assisted with CST is
performed in HB simulator (ADS environment), where layout geometry dimensions are modified for
optimum power performance. The results will be discussed in the next section. Refer to Appendix A for
the detail layout guidelines. The photograph of the DPA is in Figure 6.18. The DPA board size area is
38 mm × 20 mm.
RF & DC routing
Layer 1
0.254 mm 4350B CORE 1/1 oz
2 sheets 0.1mm 4450B PPG
Grounding for microstrip traces
0.421 mm 4350B CORE 1/1 oz
Layer 2
DC lines
Layer 3
Via-hole
2 sheets 0.1mm 4450B PPG
0.254 mm 4350B CORE 1/1 oz
Bottom solid grounding
Layer 4
Figure 6.17: 4-layer high density Rogers PCB; metal Layer 1 and 4 thickness is 0.06 mm, and
Layer 2 and 3 having thickness of 0.035 mm, and thus, total PCB thickness is ~1.4 mm.
58
The asymmetric dielectric properties i.e. 2 sheets 4450B and core 4350B Rogers are embedded between of the inner metal
layers (as shown in Figure 6.17) to avoid PCB warping issue. This recommended by Motorola.
59
The indium foil is received from Indium Corporation, and thermal conductivity of the copper foil is 0.34W/cm at 85 °C. The foil part
number is IN52-48SN (0.004" thickness), Indium Corporation Inc., North Carolina, US
111
Vd 1
Vd3
Vd2
RFin
RFout
20 mm
Power
high-fτ
transistor
transistors
38 mm
Vg3
Vg1
Vg2
Figure 6.18: Photograph of the prototype of DPA having high-fτ transistors cascaded to the power
transistor with inter-stage impedance termination. The DPA size area is 38 mm × 22 mm.
C. Measurement Results
Supply voltages of 5.5 V and 28 V are applied to the high-fτ transistors and to the power transistor,
respectively. The high-fτ transistors are biased with IDQ of 34 mA (20%Idss) and 93 mA (14%Idss), and
power transistor with 188 mA (4%Idss), respectively. For GaN HEMT device, important issue is the biasing
sequence. The goal while biasing the device is to stay away from areas of sensitive to the potential
instability of the device. One needs to pay attention to how to deal with a positive gate current which will
arise when the device is drive into saturation, and to overcome this limitation is to use a resistor
connected across the power supply terminals, the resistor will enable the power supply to always provide
a negative current while allowing the device to source or sink current [178].
The measured results of S-parameter is shown in Figure 6.19, the output return loss S22 is <-6 dB and
input return loss S11 is <-10 dB across bandwidth. One should take note that S22 is higher than -10 dB
across the bandwidth, and this is because the dummy termination is eliminated to maximize power 50 Ω
load. Due to the reason output DPA will be coupled to the harmonic filter 60 in real application, and the
reflection matching can be improved. Reverse isolation S12 performance is better than -50 dB over the
entire bandwidth operation. The measured output power, gain and efficiency of the DA versus frequency
with initial design (without any optimization) are shown in Figure 6.20. Output power of 10 W, 32 dB gain
and PAE >15% across bandwidth are recorded in measurement level, shown in Figure 6.20. As can be
observed in Figure 6.20, output power is quite flat (10 W) beyond 1.3 GHz, and has slight degradation
beyond 1.3 GHz due to grounding effect of the GaN device (as discussed in the previous section).
However, good correlation between simulation and measurements is achieved through a full-wave EM
modeling of the complete structure.
The power performance (i.e. power, gain and PAE) has been characterized at 1GHz by sweeping the
input drive Pin, and the plot is shown in Figure 6.21. The optimum power performance is occurred at Pin of
10 dBm. RF drive tracking from [188] can be applied to this DPA for optimum performance. According to
researcher’s knowledge these results demonstrated best performances in output power-gain response
within operating bandwidth up to 2 GHz. This work has achieved a high output power and high gain
simultaneously with a low cost implementation technology, and consumes reasonable small size area.
A stability test with termination of 4:1 VSWR was carried out. Implementation of capacitors at drain line
i.e. 22 uF tantalum capacitor 61 , and 33 pF, 470 pF and 22 nF (ceramic capacitors from Murata Inc.) took
60
Example of harmonic filtering design is given in section 2.4.
The tantalum capacitor of 22 uF is received from Vishay Inc. (part number is 595D226X0050R2T) and the operating voltage is
60 V.
61
112
place in the PCB as a precaution of low frequency parasitic oscillation. No oscillation is reported and the
DPA operation is very stable. Figure 6.22 shows example of spectra graph at 400 MHz.
S -param eter [dB ]
60
20
-20
-60
S21- Simulated
S22 - Simulated
S12 - Simulated
S11- Simulated
-100
-140
0
0.5
1
1.5
2
Frequency [GHz]
S21- M easured
S22 - M easured
S12 -M easured
S11- M easured
2.5
3
Power [dBm], Gain [dB] & PAE [%]
Figure 6.19: Measured vs. simulated of S-parameters of the DPA having high-fτ transistors
cascaded to the power transistor with inter-stage tapered termination.
45
40
35
30
25
Power - Simulated
Power - Measured
20
PAE - Simulated
PAE - Measured
15
Gain - Simulated
Gain - Measured
10
0
500
1000
1500
Frequency [MHz]
2000
Figure 6.20: Measured vs. simulated of power performance of the DPA having high-fτ transistors
cascaded to the power transistor with inter-stage tapered termination.
113
Power [dBm] & PAE [%]
45
40
35
30
25
20
Power
PAE
Gain
15
10
0
2
4
6
8
Pin [dBm]
10
12
Figure 6.21: Measured results of power performance i.e. power and PAE with sweeping the Pin
drive (at 1 GHz) of the DPA having high-fτ transistors cascaded to the power transistor with
inter-stage tapered termination.
Figure 6.22: Example of measured of power spectra at 400 MHz and there is no oscillation is
reported. The output signal is attenuated with external 30 dB attenuation pad to avoid damage to
the spectrum analyzer.
6.2 Second DPA development
6.2.1
Motivation
The motivation of this section is to design higher output power, gain and efficient DPA for SDR PA
applications, and the operating bandwidth up to 2 GHz. Due to loading effect of the bigger size transistor,
114
DC-RF energy conversion is not optimum as the frequency increases towards cut-off frequency. These
amplifiers, in fact, have never exhibited output power more than 10 W [11], [12], [104]. GaN HEMT grown
in SiC substrate is favorable device candidate for high output power [12], [16], [167], [175] besides
LDMOS, GaAs HBT, pHEMT and SiGe HBT process [11], [83], [91]. The state-of-art of the
power-bandwidth of the DPA works is summarized in Figure 6.23. The work by [14] demonstrated best
performance in output power-gain response within an operating bandwidth up to 2 GHz. However, this
section is focus to achieve output power of ~20 W (or more) over the frequency range up to 2 GHz [13],
[15].
Loading effect of drain line becomes stronger with bigger device periphery, and typically attenuation
compensation technique is used, where an active load (common-gate FET) is coupled to the
common-source FET to reduce the drain line losses dominated by the real part Ropt [169]. Some literature
called this technique as cascode DA [168], [171]. However, this technique in principle offers higher output
impedance and improving reverse isolation, but additional FET device and biasing gate circuitry to
common-gate are needed. Nevertheless, this is a good solution for MMIC approach [168].
In the following section, a new technique to achieve current combining to a single load termination while
preserving power match condition to each device section will be discussed. This technique is so called
vectorially combined current sources with load pull determination [13], [15]. The advantage of the
technique is each device having an optimum DC-RF conversion (like single ended PA device), when
loaded in distributed input/output networks, and the drawback is, an impedance transformation to 50 Ω is
required. However, In the end of the chapter, design methodology of a broadband impedance transformer
in small size area realization by means Real-Frequency Technique (RFT) is explained [26] – [27].
Section 7.2 reviews the circuit principle of cascode DA, and to achieve high output power without
impedance transformer. Combination of cascode GaN DA with power match/current combining technique
is new in principle, which will definitely interesting for future works.
Power, W
50
with load pull
determination
[15], [13]
20
10
7.5
5
with 50 Ω
termination
Device from
Freescale
[11], [14],
GaN HEMT
LDMOS
pHEMT
[12]
GaAs HBT
SiGe HBT
2.5
[167]
[16]
[115]
[11]
[91]
[138]
2
1
[168]
10
15
fc, GHz
20
Figure 6.23: Summarized state-of-art work of output power-frequency DPA.
115
6.2.2
Concept of Vectorially combined current sources with load pull determination
In order to maximize power Po from each transistor section (as shown in Figure 6.24), each current
source should be loaded with an optimum load impedance Ropt’ (for optimum excursion RF voltage
Vmax/Imax current swing) [111]. In order to utilize the Vmax and Imax, which is known as power match
condition, an optimum lower value of Rload would be selected to provide loadline match, Ropt’ = Vmax/Imax
[111], as shown in Figure 6.24. It has been assumed that Rgen (i.e. Rds) >> Ropt’ if Rgen is taken into
account, it would be necessary to solve the equivalent impedance (Rgen // Ropt’). The effective real part of
the device at reference plane A (Ropt’) and B (Ropt) is different due to the fact of its shunt capacitance and
package parasitic effect, as explained in Figure 3.24 (b). In real application, it is convenient to identify the
real part of the device at reference plane B which will be used to match to standard output termination
(e.g. 50 Ω load). The optimum impedance of the transistor Zopt(ω) (consists of real and imaginary
part) can be extracted by means of non-linear load pull technique [111] either by simulation or
measurement, which generally has frequency-dependency behavior.
As a generally confirmed by experimental results on FETs, the the optimum reactive part Xopt(ω) to be
absorbed in the distributed output drain line network is almost equivalent to a constant capacitance Copt
over very wide bandwidths in MMIC implementation [168], and may have non uniform value in hybrid
packaged implementation. Nevertheless, in the hybrid implementation, Xopt(ω) i.e. intrinsic parasitic
capacitances, extrinsic elements, packaging effect, etc, and the power optimization consists of loading
the equivalent output source of the transistor with optimum power load Ropt(ω) .
One must bear in mind that to combine multi current sources to a single load termination, an optimum
virtual impedance to each source in two directions i.e. Zu(k) and Zr(k) must be fulfilled (as discussed in
section 4.2). The generalized design equations developed in section 4.3 are not sufficient when device
current source is loaded by Ropt(ω). In this section, a technique concept to achieve power match to each
source while satisfying multi current sources combining to a single load termination is presented.
Figure 6.25 shows a simple schematic of two current sources combined at a common node connected to
a load RL, and each current source is loaded with optimum power load Ropt(ω). As shown in Figure 6.25,
the virtual impedance Zu(1) looking into common node with i2(t) in parallel with Ropt(ω) and load termination
RL is what current source vector i1(t) is loaded with. Applying Thevenin theorem to Figure 6.25, thus the
impedance Zu(1) can be derived as
Z u (1) = v (t ) / i1 (t ) =
[i1 (t ) + i2 (t )]
(0.5 Ropt // RL ) .
i1 (t )
(6.13)
Ropt’ = Vmax/Imax, assuming Rgen >> Ropt
+
Imax
Vmax
Rgen
Ropt’
device
Figure 6.24: Optimum power condition of the device current source loaded by Ropt.
116
By substituting ik
= I k e j ( wt +θ k ) , where k = 1 and 2, one can derive the virtual impedance
⎡ I
⎤
Z u (1) = 0.5Ropt // RL ⎢1 + 2 (cos(θ 2 − θ1 ) + j sin(θ 2 − θ1 ) )⎥ ,
⎣ I1
⎦
(6.14)
where I1 and I2 representing magnitude of the complex current source and θ1 and θ2 are independent
phase value, respectively.
In this section, phase offset or in-phase combining (θ2 = θ1) is considered to simplify the concept, and the
concept can be easily explain for θ2 ≠ θ1. (6.14) can be simplified as
Z u (1) = (1 +
I2
)(0.5 Ropt // RL ) .
I1
(6.15)
From (6.15), the virtual impedance Zu(1) seen by the current source i1(t) is directly depending on RL and
I2/I1. As an example, for equal injection value I2/I1 = 1 (equal device periphery), Zu(1) ≈ Ropt when RL is set
to ≥10Ropt. The selection of RL reveals what characteristic impedance of transmission line Zr(1) to be
designed. It should be noted that the virtual impedance seen by current source i.e. Zu(1) must be close to
Ropt while both current sources are combined at single load RL, then this met criteria of power
match/current combining conditions. Nevertheless, Zr(1) will absorb the imaginary part Xopt to form
broadband frequency operation.
Zu(1)
i1(t)
Zr(1)
+
v(t) Ropt(ω)
RL
Ropt(ω)
i2(t)
-
Figure 6.25: The virtual impedance seen by the current source i1(t) in both directions Zu(1) and Zr(1),
respectively when two current sources are combined to a single node.
In similar manner, one can derive Zu(k) , k = 1, 2,..,n, as shown in Figure 6.26 as below
Zu(k ) = (
I1 I 2 I 3
I
+ + + .. + n )( Ropt 1 // Ropt 2 // .. // Roptn // RL ) .
Ik Ik Ik
Ik
(6.16)
Lets review the analysis for n section, and identical device periphery are selected,
Zu(1) = Zu(2) = Zu(3) ≈ Ropt // ZL, and it can be approximated to Ropt if ZL has reasonable termination.
Figure 6.26 shows drain transmission line Zr(k) must be synthesized to load each device generator by its
117
optimum Ropt(k)(ω), where k = 1,2,..,n. It is clear from Figure 6.26 that Zr(1) must be loaded with optimum
load resistive of the first generator Ropt1 and Zr(n) should be loaded with ZL value. Nevertheless, the middle
section e.g. Zr(2) is depending on Zu(2) and Zu(3). It is necessary to know the initial value of Ropt1, which
typically can be obtained with single device load pull determination. In similar way, ZL must be performed
with initial guess of Zr(1),..,Zr(n). To obtain the initial guess, it is convenient to use CAD simulator assisted
with optimizer (e.g. ADS), where the transistor is modeled with an ideal current source and parallel high
impedance resistor. To additively combine the currents at each junction, phase synchronization between
the current source and the transmission line delay i.e. Zr(k) is matched. From design equations of an
optimum virtual impedance to each source in two directions i.e. Zu(k) and Zr(k) have behavior that
adaptively reducing towards load termination. For example, Zr(1) = 50 Ω, Zr(2) = 25 Ω, Zr(3) = 16.7 Ω and
Zr(4) = 12.5 Ω is achieved if no loading effect taken into considerations. Therefore, one may call this DPA
as vectorially combined current sources with load pull determination.
Zr(1)
Zr(2)
Zu(1)
i1(t)
Ropt1(ω)
Zr(n)
Zu(2)
i2(t)
Zu(n)
Ropt2(ω)
in(t)
Roptn(ω)
ZL
Figure 6.26: Synthesize drain transmission line to load each device generator by its optimum
Ropt(k)(ω).
6.2.3 Design and Measurement Prototype
A. Objective
The objective of this work is to achieve high power, efficiency and gain covering bandwidth operation of
10-2000 MHz, so that the DPA system can be coupled directly to VCO (Voltage Controlled Oscillator).
The VCO output is typically ~8 dBm, and the output power of 30 W 62 is the design goal over the entire
bandwidth operation (40 - 2000 MHz). Thus, gain of 37 dB is required to deliver high output power
i.e. 30 W. The efficiency must be more than 35% across bandwidth. Refer to Table 6.3 for the design goal
requirement of this work.
B. Design Example and Layout Considerations
High-fτ transistor with lowest input parasitic capacitance Cgs i.e. ATF54143 device is coupled to the gate
line, and this may improve the loading effect of input gate line. The achievement of high gain in the
40-2000 MHz operating range is adopted from section 6.2.2, allowing the resulting DPA to be coupled
directly to the VCO. Each section having two non-identical high-fτ transistors (ATF54143 and
63
ATF511P8) , respectively from Avago Inc. which are cascaded to the power transistor (GaN device from
CREE Inc.), with inter-stage tapered impedance. As discussed earlier, optimum number of section n to
maximize power at any frequency is 3..4 [21], therefore, 3 sections are used in this design to deliver 30 W
output power (assuming each GaN device contributing ~10 W). The general diagram of the DPA topology
is shown in Figure 6.27. The term n and N are referring to number of stages in cascaded and section,
respectively.
62
Output power of 30 W is typically used for base-station or mobile PA applications.
Gate-periphery of ATF54143 and ATF511P8 are featured by 800µm and 6400µm, respectively, and the same devices are used
in section 6.2.2.
63
118
Parameter
Bandwidth
Output power
Gain
PAE
Goal
40 MHz - 2000 MHz
30 W
37 dB
35%
Table 6.3: Design goal requirement of second DPA.
IN
L g1
n - s e c tio n
M1
Q1
Mn
Qn
Po w e r
tra n s is to r
L g2
Ld 1
M1
Q1
L g3
Mn
Qn
Po w e r
tra n s is to r
Ld 2
N - s e c tio n
Mn
M1
Q1
Qn
T e rm t .
P o w er
t ra ns is to r
Ld n
Im p e d a n ce
tr a n sfo r m e r
OUT
Figure 6.27: General diagram of high power DPA circuit proposal. The term n and N are referring
to number of stages in cascaded and section, respectively. Impedance transformer may included
when the termination is less than 50 Ω.
As discussed in section 3.4, the design methodology i.e. from device selection, synthesizing gate/drain
line elements from device packaged values, until full-wave simulation/layout optimizations are applied in
this section. GaN device (CGH40010F) is used in this work, and Vbk of the device is ~73 V. The drain
loading effect of the device is very significant. Effective input and output real and imaginary part of the
packaged devices Xin(ω) and Xopt(ω) (of high-fτ and power transistors), respectively are extracted as
explained in section 3.4, and the values are tabulated in Table 3.1. For instance, Xopt(ω) of the second
output high-fτ transistor will be matched to the Xin(ω) of the input power transistor (GaN device) by means
of theoretical approach presented in section 6.1.2.
The effective input capacitance of the first high-fτ transistor Cin and effective output capacitance of the
power transistor Cout are important to form ωc. As shown in Table 3.1, the effective input capacitance of
the first high-fτ transistor and output capacitance of the power transistor are lower than 3 pF, which
means ωc of 2.2 GHz can be formed with 50 Ω load, refer to (3.6). Therefore, effective gate and drain line
elements i.e. Li are synthesize by means of (3.48) to form desired the ωc. Dummy drain termination is
eliminated to improve the efficiency performance [16]. To achieve 30 W output power, PAE >35% and
gain more than 35 dB (since input drive is ~8 dBm), and to achieve bandwidth up to 2.2 GHz, N = 3 and
n = 3 are proposed. It is important to note that DPA gain-bandwidth response is dominated by the gate
line and cascaded stages, while power-efficiency response is mainly contributed by the drain line.
Therefore, design work focused to synthesize the gate line network, inter-stage tapered impedance, and
followed by drain line network to achieve power performance for broadband range up to 2 GHz. An
119
approach as demonstrated in [83] is adopted for the gate line, whereby phase synchronization is
achieved with non-uniform gate line design and the gate line impedance is adaptively reduced. Power
match and current combining technique is implemented at the drain line.
DC bias networks including gate and drain feeding design for each high-fτ transistor from section 3.3,
where Lg-Cg and Ld-Cd networks from Figure 3.20 are implemented. Integration the DC bias network to
the DPA topology is necessary while satisfying the RF to DC isolation over the wide bandwidth response.
It is beneficial to measure RF to DC isolation over wide frequency response of the DPA to ensure the
64
design of broadband bias networks. For the first and second high-fτ transistors, Ld and Cd of 180 nH
65
and 33 pF , respectively are selected for bandwidth operation up to 2 GHz [11].
The DC gate biasing terminals are bypassed to ground with multiple chip capacitors (e.g. 100 pF, 33 nF,
66
10 uF, etc) for each transistor. For the DC feeding lines for final stage is connected to high Q air-wound
67
68
coil (from Coilcraft Inc.) , and high Q chip inductors (value of 220 nH) for first and second stage from
Coilcraft Inc. Photograph of the new DPA topology is shown in Figure 6.33. Effective DPA size area is
38 mm × 32 mm.
To begin the drain line synthesis, it is important to identify Ropt of the power transistor for optimum DC-RF
energy conversion. For single ended DC-RF energy conversion of the power transistor (CGH40010F),
Ropt(ω) ≈ 40 Ω (average value across bandwidth) is obtained from load pull simulation technique. One
should bear in mind that the optimum load impedance has frequency dependency behavior. Hence,
Zr(1) ≈ 40 Ω, and Zr(2) and Zr(3) ≈ ZL are optimized in CAD simulator, for optimum power performance up to
2 GHz, refer to Figure 6.28 for the drain line synthesis. Simplified design schematic of the new DPA
topology is shown in Figure 6.29.
Zr(1)
Zr(2)
Zu(1)
i1(t)
Zr(3)
Zu(3)
Zu(2)
Ropt1(ω)
i2(t)
Ropt2(ω)
i3(t)
Ropt3(ω)
ZL
Figure 6.28: Synthesize drain transmission line to load each device generator by its optimum
Ropt(k)(ω) for n = 3. ZL is identified for optimum power performance in CAD simulator.
To verify the design example, simulation with Harmonic Balance (HB) 69 is carried out to understand its
70
power performance. The non-linear models of the devices, and passive elements model
were
developed by Modelithics Inc. Supply voltages of 5.5 V and 28 V are applied to the high-fτ transistors and
to the power transistor, respectively. The high-fτ transistors are biased with IDQ of 34 mA (20%Idss) and
64
The high-Q ceramic 0603HP series chip inductors provided by Coilcraft Inc., and the Q up to ~150 at 1.7 GHz.
This is broadband high-Q capacitor 3060 size from Murata Inc, and details can be obtained at www.murata.com.
66
The capacitors are referring to 600S Series Ultra-Low ESR, high Q microwave capacitors, from ATC Inc., and the series is 545-L
ultra-broadband capacitor, from Murata Inc.
67
The electrical specification of the broadband choke: L = 1.3 uH ± 10%, DCR = 12.6 mΩ, Irms = 4 A, and this product is preliminary
version (part number is JA4643-AL)
68
The series of the choke is 0603CS_XNL (1008HS), from Coilcraft Inc.
69
The first attempt of the simulation excluded layout structure considerations, but the final simulation is optimized with ADS
Co-Simulation (CST) assisted with HB.
70
All the device and passive models are developed by Modelithics Inc., except for the GaN device model is performed at ITHE,
RWTH Aachen.
65
120
93 mA (14%Idss), and power transistor with 188 mA (4%Idss), respectively. The input drive throughout the
measurement level is fixed to low level (~8 dBm).
The simulated results of S-parameter and power performance i.e. power, PAE and gain are shown in
Figure 6.30 and Figure 6.31, respectively. The small-signal gain S21 is quite flat over the frequency range
(about 40 dB) and small peaking is occurred outside the band. Good reverse isolation S12 of the DPA is
more than -60 dB, and input and output return loss is better than -10 dB, respectively over the frequency.
The large-signal performance i.e. output power is achieved constant 45 dBm (30W), flat gain of 37 dB up
to 2 GHz. PAE is more than 40%, but in general average PAE is ~52% is achieved in simulation level.
Input from
VCO
Cx1
Lx1
Cm1 Lx1
Zti , i=1,..,6
Cd1c
Zg1
Cd1b
Cd1a
Zr(1)
Zt4
Zt1
Cd2c
Zg2
Cd2b
Cd2a
Zr(2)
Zt5
Zt2
Cd3c
Zg3
Cd3b
Cd3a
Zr(3)
Zt6
Zt3
Output
terminated to
ZL
Zg4
Dummy
termination
high-fτ
transistors
power
transistors
Figure 6.29: Simplified schematic the new DPA topology. The input drive of the VCO is ~8 dBm,
and non-uniform gate line is adopted from [19]. Two non-identical high-fτ transistors (ATF54143
and ATF511P8) are cascaded to the power transistor (GaN device). Output impedance is
terminated to ZL, which will be coupled to transformer/filter 71 .
`
71
The design of transformer/filter will be discussed in section 6.2.4.
121
S-parameter [dB]
60
20
-20
-60
-100
S21- Simulated
S22 - Simulated
S12 - Simulated
S11- Simulated
-140
0
0.5
1
1.5
2
Frequency [GHz]
2.5
3
Power [dBm], Gain [dB] & PAE [%]
Figure 6.30: Simulation analysis of S-parameters for the new topology DPA across 0.1-2 GHz, and
ZL of ~14 Ω is required for optimum performance.
70
60
50
40
30
Gain
20
PAE
Power
10
0
0.4
0.8
1.2
1.6
2
2.4
Frequency [GHz]
Figure 6.31: Simulation analysis of power performance i.e. power, gain, PAE for the new topology
DPA across 0.01-2 GHz, and ZL of ~14 Ω is required for optimum performance.
In order to experimentally validate the concept technique, a prototype board of the design is using Rogers
4350/4450B PCB material is used. The same layer structure as shown in Figure 6.17 is used. Since
additional DC routing is needed to connect each gate of high-fτ and power transistors, thus, layer 3 is
used. Open grounding area with adequate via-hole, and DC and RF routing are well isolated in PCB for
minimum spurious. As part of EMC requirements, it is necessary to have DC layer below RF grounding
layer [88]. Hence, layer 2 and layer 4 have solid grounding plane. Thickness of the DC routing is
computed to carry adequate DC current, and the width thickness is shown in Figure 6.32. For an example
in layer 3, most thick routing (yellow color) is used for drain supply of second high-fτ transistor, and
routing with red color is for drain supply of first high-fτ transistor. Layout artwork of the DPA topology (for
all layers from Cadence) is given in Figure 6.32.
122
(a) Top layer
(c) Layer 3
(b) Layer 2
(d) Bottom layer
Figure 6.32: Layout artwork of the DPA topology for all layers. Additional DC routing is done via
layer 3, where layer 2 is RF grounding.
Two diameter screws, which are 5 mm and 1.4 mm, are mounted to hold the grounded heat-sink chasis.
The modeling of the screws and the foil are reused (from section 6.2.3), and the RF connector (from
section 4.4.3) is reused. The inductance of the gate and drain lines are realized in lumped transmission
line with aid of CST. The layout structure (from Figure 6.17) was imported from Cadence, and the line
properties i.e. length and width shall be optimized for optimum value of inductance and Q-factor over wide
frequency range. Due to the fact the length is fixed (because of power transistor length dimension to
9.5 mm), therefore, only the width will be optimized. From the CST simulation, self resonance of the line is
72
kept higher than 4 GHz for uniform result of inductance and reasonable high Q-factor .
72
Q-factor is defined by center frequency over bandwidth operation. Q-factor of 500 is required
123
RFin
high-fτ
Power
transistors transistor
Vd1
38 mm
Vd2
GND
Vd 3
32 mm
Vg1
Vg2
Vg3
RFout
Load pull
measured at a’
Figure 6.33: Photograph of the prototype of new topology DPA. The DPA size area is
38 mm × 32 mm.
C. Measurement Results
Supply voltages of 5.5 V and 28 V are applied to the high-fτ transistors and to the power transistor,
respectively. The high-fτ transistors are biased with IDQ of 34 mA (20%Idss) and 93 mA (14%Idss), and
power transistor with 188 mA (4%Idss), respectively. The input drive throughout the measurement level is
fixed to low level (~8 dBm). For GaN HEMT device, important issue is the biasing sequence. The
importance while biasing the device is to stay away from areas of sensitive to the potential instability of
the device. One needs to pay attention to how to deal with a positive gate current which will arise when
the device is drive into saturation, and to overcome this limitation is to use a resistor connected across
the power supply terminals, the resistor will enable the power supply to always provide a negative current
while allowing the device to source or sink current [178].
Firstly, the measurement work of the prototype board was started with identification of optimum load
73
impedance to be terminated at point a’ (shown in Figure 6.36). Test fixture of the line calibration is build
to deembed the transmission line length. Figure 6.37 shows the example measured results of load pull
impedance contour for 100 MHz and 1 GHz, respectively. The highest power is recorded at impedance of
25+j39 Ω and 25-j18 Ω for 100 MHz (40 W) and 1.9 GHz (25 W), respectively, shown in Figure 6.34. The
imaginary impedance data indicated that at low frequency the line has higher capacitance and varies to
inductance as the frequency increases. Figure 6.35 shows the comparison between measured vs.
simulated of highest output power with load pull technique across the bandwidth. However, the optimum
performance (output power, gain and PAE) is achieved at ~12 Ω region in measured level across the
entire bandwidth, refer to Figure 6.36. The output of 25 W, and PAE results of 45-56 % are recorded in
measurement level, while flat response of operating gain is obtained. Although some imaginary part
exists (the variation ±j4 Ω), therefore, real part of 12 Ω is sufficient to be terminated at the output of the
DPA. The following section will explain on designing of broadband transformer (12 Ω to 50 Ω) with
minimum insertion loss (~1 dB) within the operating bandwidth frequency.
With the same prototype board, measurement with 50 Ω termination is carried out to understand its
performance. Measured vs. simulated results of S-parameter and power performance of the topology
terminated to 50 Ω are presented in Figure 6.37 and Figure 6.38, respectively. Output return loss S22 is
<-8 dB and input return loss S11 is <-12 dB across bandwidth. One should bear in mind that S22 is higher
73
Thru, reflect and line (TRL) calibration is standard calibration for load pull determination system
124
than -10 dB across the bandwidth, and this is because the dummy termination is eliminated to push all
the current from each device to a single load termination. As the results, output reflection matching is not
well optimized. The measured isolation S12 is about 60 dB, and small signal gain S21 is more than 40 dB
across bandwidth. There is no small signal peaking is recorded in measurement (near ωc), although small
in value is observed in simulation level. Output power of ~15 W, with PAE of 15-42 % is recorded in
measurement level with 50 Ω termination. At 50 Ω termination, the highest output power is 18 W at low
frequency, and at 2 GHz, the power degraded to 10 W.
Since all the measurement were done with low input drive to meet SDR applications, power
characterization (power and PAE) at 1 GHz by sweeping input drive is carried out, and shown in
Figure 6.39. The results indicated that the output can hit ~18 W and PAE of 34% with 50 Ω termination.
The optimum power happened at input drive of ~10 dBm (slightly higher than output level from VCO
capability). One should keep in mind that input drive required to the DA may change with frequency
behavior. As the frequency increases, higher drive is needed. Therefore, a RF input drive adjustment
circuitry to provide adequate RF signal strength to the DA under constant envelope modulation [190] can
be implemented.
74
Implementation of capacitors at drain line i.e. 22 μF (tantalum capacitor) and 10 pF, 33 pF, 470 pF and
22 nF (ceramic capacitors) take place as a precaution of low frequency parasitic oscillation. No oscillation
is reported and the DPA operation is very stable with 50 Ω termination. Nevertheless, further work of
stability check with 4:1 VSWR will be carried out.
Maximum power region
Optimum performance
region
Maximum power region
Optimum performance
region
(a)
(b)
Figure 6.34: Example of measurement results of load pull impedance determination for 100 MHz
and 1 GHz, respectively. The maximum power occurred at ℜ{ZL} of 25 Ω.
74
The tantalum capacitor of 22 uF is received from Vishay Inc. (part number is 595D226X0050R2T) and the operating voltage is
60 V.
125
45
40
Power [W]
35
30
25
20
Max. Power - Measured
15
Max. Power - Simulated
10
0
400
800
1200
1600
Frequency [MHz]
2000
2400
Figure 6.35: Measurement results of highest output power with load pull impedance determination
across the entire bandwidth. The maximum power occurred at ℜ{ZL} of ~25 Ω in measured level.
Power [W], PAE [%], Gain [dB]
70
Power - Measured
Power - Simulated
PAE - Measured
PAE - Simulated
Gain - Measured
Gain - Simulated
60
50
40
30
20
10
0
400
800
1200
1600
Frequency [MHz]
2000
2400
Figure 6.36: Measurement results of optimum power performance i.e. power, gain and PAE with
load pull impedance determination across the entire bandwidth. The maximum power occurred at
ℜ{ZL} of ~12 Ω in measured level.
126
S-param eter [dB]
60
20
-20
-60
S21- Simulated
S22 - Simulated
S12 - Simulated
S11- Simulated
-100
S21- M easured
S22 - M easured
S12 - M easured
S11- M easured
-140
0
0.5
1
1.5
2
Frequency [GHz]
2.5
3
Figure 6.37: Measured vs. simulated of S-parameters of the DPA topology terminated to 50 Ω
load.
Power [W], Gain [dB] & PAE [%]
50
40
30
20
10
Power - Measured
PAE - Measured
Gain - Measured
Power - Simulated
PAE - Simulated
Gain - Simulated
0
0
400
800
1200
1600
Frequency [MHz]
2000
2400
Figure 6.38: Measured vs. simulated of power performance of the DPA topology terminated to
50 Ω load.
127
45
Power [dBm] & PAE [%]
40
35
30
25
20
Power
PAE
Gain
15
10
0
2
4
6
8
Pin [dBm]
10
12
Figure 6.39: Measured results of power performance i.e. power and PAE with sweeping the Pin
drive (at 1 GHz) of the new DPA topology.
Good correlation between simulation and measurements is achieved through ADS momentum modeling
of the complete layout structure. The summary of power performance i.e. output power, PAE and gain are
tabulated in Table 6.4. According to researcher’s knowledge these results demonstrated best
performances in output power, gain and efficiency response within operating bandwidth up to 2.2 GHz.
This work has achieved a highest power performance with a low cost implementation technology, and
consumes reasonably a small size area.
This work
[13], [15]
Zhao et al.
[11]
Gassmann et al.
[12]
Xie et al.
[104]
Fraysse et
al. [168]
Lin et al.
[175]
Power
>43 dBm
>35 dBm
>37 dBm
>39 dBm
34 dBm
>37 dBm
Gain
32 dB
9 dB
7 dB
12 dB
9 dB
11 dB
PAE
18-43 %
>20%
30-70%
30-70%
>20%
>27%
BW
0.04-2 GHz
0.1-2 GHz
2-15 GHz
0.02-2 GHz
2-8 GHz
0.02-3 GHz
Num.
section
3
5
5
4
6
3
Fabricated
Hybrid
Hybrid
MMIC
Hybrid
MMIC
hybrid
Device
pHEMT +
GaN HEMT
LDMOS
GaN HEMT
GaN HEMT
HBT
GaN HEMT
Table 6.4: Summary performance of the new DPA topology.
6.2.4
Real-Frequency Broadband Transformer/Filter
6.2.4.1 Motivation
In designing wideband communication systems, usage of impedance transformers and filters are
inevitable. Usually, filters are designed between resistive terminations say R1 and R2 to restrict the
128
frequency band of operations. As shown in Figure 6.40, R1 designates the idealized internal resistance of
the Thevenin driving source EG the load which dissipates transferred signal power PL over the prescribed
frequency band of operation [179] – [183]. In practice, the source side may represent the output of an
amplifier which may be a low resistance such as R1 = 12 Ω, and the load may be a standard termination
like R2 = 50 Ω.
.
Gain Characteristics of Monotone Rolloff Chebyshev Filters
1.1
T0=1
1
0.9
EG
[F]
R2
TPG of the filter
0.8
R1
0.7
0.6
0.5
n=7 case
n=6 case
0.4
0.3
0.2
0.1
0.2
0.4
0.6
0.8
1
1.2
1.4
Normalized Angular Frequency W
1.6
1.8
2
Figure 6.40: Basic topology of bipolar Class E power amplifier with shunt capacitance circuit.
In the classical filter literature [179] – [183], it is well established that passband filters are constructed
based on the lowpass prototype using lowpass to band pass transformations which in turn doubles the
number of elements of the original lowpass prototype. For many RF applications, it is customary to design
a lossless two-port which transforms a resistive termination R1 to R2 to provide maximum power transfer
over a prescribed band of operation as shown in Figure 6.41. This configuration is neither an ideal
transformer nor an ideal filter. It is the combination of both. Hence, we call it transformer/filter.
R1 ≠ R2
Figure 6.41: An ideal Transformer with a filter which constitutes a “transformer/filter”.
While transforming resistance R1 to R2, an ideal transformer/filter must have a flat transducer power gain
T0 = 1 over the passband B = f2 – f1; or equivalently over the angular frequency band B(ω) = ω2 – ω1 as
depicted in Figure 6.42. In these descriptions, f2 and f1 are the upper and the lower cutoff frequencies of
transformer/filter and the angular cutoff frequencies are specified by ω2 = 2πf1 and ω2 = 2πf2.
T0 = 1
R1 ≠ R 2
ω1
ω2
ω
Figure 6.42: An ideal transformer/filter with Transducer power gain (TPG) characteristics.
129
To the researcher’s knowledge, there is no known analytic form of a lowpass prototype transfer function
which approximates the idealized characteristic of a transformer/filter as concluded above. In practice
however, transformer/filter can be designed using readily available CAD tools such as Spice, AWR, ADS,
etc. In the design process, the user first selects a proper circuit topology with unknown element values,
then, initializes the element values. Eventually, using a non-linear optimization algorithm, unknown
element values are determined to approximate the ideal transducer gain characteristic as shown in Figure
6.45. When dealing with a few elements in the circuit topology, say up to 3 elements, this ordinary
approach may be sufficient to construct narrow bandwidth transformer/filter. Unfortunately, if the
bandwidth becomes wide enough, optimization process becomes highly non-linear in terms of the
element values. In this case, one needs to employ state of the art approaches such as real frequency
techniques [179] – [183].
6.2.4.2 Real-Frequency Design of a Transformer-Filter
This chapter desires to design a transformer/filter to transform a resistance R1 = 12 Ω to R1 = 50 Ω over
100 MHz to 2.2 GHz bandwidth. In fact, in this problem, R1 = 12 Ω represents the output resistance of a
distributed amplifier which is supposed to deliver its maximum power to a standard 50Ω termination.
Hence, we face a typical design problem of a transformer/filter over a wide frequency band. In the course
of design process, we try to use readily available CAD tools by selecting proper circuit topology. Due to
the highly non-linear nature of the problem, optimization scheme of the design was not successful.
Eventually, we employed the Real Frequency Direct Computational Technique (RF-DCT) which yields an
excellent solution for the transformer/filter problem under consideration. RF-DCT may be considered as a
semi-analytic procedure to construct lossless two-ports for a pre-assigned gain performance [184] - [186].
Referring to Figure 6.43, in RF-DCT, the lossless transformer/filter is fully described in terms of its
Darlington’s driving point impedance. Darlington proved that any positive real impedance can be realized
as a lossless two-port in resistive termination [184].
Z B ( p) =
N ( p)
= Z M ( p) + Z F ( p)
D( p )
Figure 6.43: Darlington’s description of lossless two-port transformer/filter, where p = σ + jω
(complex variable) [184].
In the present case, ZB (p) must be determined to approximate the idealized transformer/filter
characteristics in such a way that, when it is synthesized in Darlington sense, the lossless
transformer/filter is obtained in desired termination R1 . Positive real (PR) impedance such as ZB (p) (from
Figure 6.43) can be expressed as the summation of a minimum reactance ZM (p) and a Foster ZF (p)
functions, ZM (p) + ZF (p).
The minimum reactance impedance function ZM (jω) is expressed as
Z M ( jω ) = RM (ω 2 ) + jX M (ω ) ,
(6.18)
where the real part RM (ω2) is a non negative even function in the angular frequency ω, and by definition,
a minimum reactance function ZM (jω) is free of Right Half Plane (RHP) and jω poles [184].
130
From the design point of view, rational form of RM (ω2) specifies the lumped element network topology for
the lossless transformer/filter when it is terminated in a resistance. The general form of RM (ω2) is given by
RM (ω 2 ) =
A1ω 2 n + A2ω 2 ( n−1) + ... + Anω 2 + An+1
≥ 0; ∀ω ,
B1ω 2 n + B2ω 2 ( n−1) + ... + Bnω 2 + 1
(6.19)
The above form corresponds to highly complicated circuit topologies depending on the values of the
numerator coefficients Ai ; i = 0. In this case, there is no way to control the termination resistance at the
far end of the synthesis. On the other hand, a simpler form is given by
RM (ω 2 ) =
R
B1ω
2n
+ B2ω
1
2 ( n −1)
+ ... + Bnω 2 + 1
≥ 0; ∀ω ,
(6.20)
which yields an n element LC lowpass ladder circuit topology terminated in ZM (0) = RM (0) = R1 as
desired.
At this point it should be noted that once RM (ω2) is specified as in (6.20), eventually, closed form of ZM (p)
of (6.21) yields the full degree rational PR function in complex variable p
Z M ( p) =
a1 p n −1 + a2 p n−2 + ... + an −2 p + an .
b1 p n + b2 p n−1 + ... + bn p + bn+1
(6.21)
Synthesis of (6.20) yields a lowpass LC ladder as shown in Figure 6.44. It is noted that the LC ladder
starts with a shunt capacitor C1 since ZM (p) is a minimum reactance function. Depending on the value of
integer n, the last component is either a capacitor Cn (n = odd case) or an inductor Ln (n = even case).
For the problem under consideration, a simpler and meaningful form of the Foster part of the driving point
impedance ZB (p) is given as
Z F ( jω ) = jX F (ω ) = −
1
ωCn+1
..
(6.22)
Then, one show deduce PR impedance of Darlington’s driving point as
Z B ( jω ) = RM + j ( X M −
1
),
ωCn+1
(6.23)
where the equations (6.21) and (6.22) fully describe a bandpass lossless two-port structure for a
transformer/filter terminated in specified resistance R1.
131
L
R1
Cn+1
L
Cn
C1
C2
Z M ( jω ) = RM + jX M Z B ( jω ) = RM + j ( X M −
R2
1
ωCn+1
)
Figure 6.44: Circuit Topology which is dictated by the real part of the Positive Real Impedance ZB.
Referring to Figure 6.42, transducer power gain of the transformer/filter is given by
T (ω ) =
4 R M R2
.
( R M + R2 ) 2 + ( X M + X F ) 2
(6.24)
Over a specified angular frequency band B (ω) = ω2 - ω1, ideally, T(ω) = 1. Thus, within the passband, let
define an error function ε(ω) such that
ε (ω ) = ( RM + R2 ) 2 + ( X M + X F ) 2 − 4 RM R 2 ,
ε (ω ) = ( RM − R2 ) 2 + ( X M + X F ) 2 ≥ 0,
ω1≤ ω ≤ ω2, or
ω1≤ ω ≤ ω2.
(6.25)
(6.26)
The crux of RF-DCT is to determine RM (ω) and XF (ω) such that the error function ε (ω) is minimized over
the band of interest [187]. Obviously, this is a non-linear optimization problem. The success of the nonlinear optimizations depends on the degree of non-linearity of the error function. If the error function is
quadratic in terms of the unknowns, it is possible to hit the global minimum; otherwise, the solution may
be complicated [187]. Now, let us investigate the degree of non-linearity of the optimization by starting
with the selected topology. In this case, let, xi designate the unknown element values the selected
topology. Then, the driving point impedance ZB (p) is expressed as
Z B ( p) =
x n +1
+
p
.
1
x1 p +
(6.27)
1
x2 p +
1
x3 p +
1
... +
1
R1
When we generate the real part RM (ω) from (6.21), it can be shown that the leading term B1 of (6.20) is
B1 = (x)x2…xn)2 which describes a 2n degree of non-linearity as oppose direct generation of B1. Similarly,
the other coefficients B2, B1,…, Bn exhibit descending degree of non-linearity {(2n-i); i = 2, 3,..n} in terms
of the unknown elements values. As far as RF-DCT is concerned, in (6.23), RM (ω) and XF (ω) are the
unknowns of the optimization problem. In other words, coefficients Bi; i = 1, 2,..,n of (6.20) are determined
to minimize ε (ω) over the passband. Once Bi is initialized, XM (ω) is evaluated by means of (6.18). In this
case, Foster part XF is selected in such a way that it practically cancels XM. That is, XM + XF ≈ 0.
132
A. Numerical evaluation of Hilbert Transformation and Real Frequency Line Segment Technique
Once RM(ω) is initialized, XM(ω) can be generated via Hilbert transformation integral. In RF-LST, the real
part is approximated by means of straight lines as shown in Figure 6.45. Let {R j , ω j ; j = 1,2,...N } be the
selected sampling points of RM(ω). In this case, RM(ω) is expressed by
⎧a ω + b j
RM (ω ) = ⎨ j
⎩ 0
where a =
j
ω j ≤ ω ≤ ω j +1 ; j = 1,2, ( N − 1)⎫ ,
⎬
ω ≥ ωN
⎭
R j − R j +1
ω j + ω j +1
=
(6.28)
( R j +1 )ω j − ( R j )ω j +1
ΔRj ; with
and ΔR j = R j +1 − R j .
bj =
ω j +1 − ω j
ω j − ω j +1
Figure 6.45: Piecewise linearization of RM(ω).
Using (6.28), Hilbert Transformation integral reveals the imaginary part XM(ω) as
N −1
X M (ω ) = ∑ B j (ω )ΔR j , such that
(6.29)
j =1
B j (ω ) =
1
π (ω1 − ω j +1 )
[ F j +1 (ω ) − F j (ω )] ,
(6.30)
with,
F j (ω ) = (ω + ω j ) ln( ω + ω j ) + (ω − ω j ) ln( ω − ω j ) .
(6.31)
It is interesting to note that, fixing rL as specified by the design problem of [T/F], transducer power gain
optimization can be carried out over the break points {R j ; j = 2,...R N −1} for the pre-fixed break frequencies
{ω j ; j = 1,2,...ω N } .
133
In this case, the error function
ε (ω ) = ( RM − R2 ) 2 + ( X M + X F ) 2 ,
Is quadratic in terms of the unknown break points {Ri ; i = 1,2,3,..., ( n − 1)} . Obviously, under the current
optimization scheme, residues of the Foster function XF(ω) of (6.22) are included among the unknowns.
Thus, RF-LST results in idealized data points for ZM(jω) = RM(ω) +jXM(ω) and the analytic form of the
Foster function XF (i.e. XF = -k0/ω). Once data points for RM(ω) is generated, it can be modeled as a nonnegative even rational function as in (10) by means of any regression algorithm which in turn leads to
analytic form of ZM(p) of (11), at this point, practical generation of minimum reactance functions become
crucial. Therefore, instead of using the integral equation from [185], it may be preferable to implement the
Parametric Approach to generate ZM(p) from RM(ω) as outlined in the following sub-section [186].
B. Approach to generate a minimum reactance function from its real part
In this method, ZM(p) is expressed in terms of its poles which are all located in the left half plane (LHP) as
follows.
Z M ( p) =
Np
a1 p n −1 + a2 p n −2 + ... + an −2 p + a n
ki .
=
R
+
∑
∞
n
n −1
b1 p + b2 p + ... + bn p + bn +1
i =1 p − p i
(6.32)
Its even part is given as
RM ( − p 2 ) =
1
[ Z M ( p ) + Z M (− p )] or
2
RM ( − p 2 ) =
n
⎡ ki
k i ⎤ ⎫ or
1⎧
+
⎨2 R∞ + ∑ ⎢
⎥⎬
− p − pi ⎦ ⎭
2⎩
i =1 ⎣ p − p i
n
⎡ k i pi ⎤ .
RM ( − p 2 ) = R∞ + ∑ ⎢
2⎥
i =1 ⎣ ( p − p i ) ⎦
(6.34)
Thus, the residues can directly be computed from (6.34) as
( p 2 − pi )( RM (− p 2 ))
pi
2
ki =
,
(6.35)
p = pi
with
R∞ = RM ( − p 2 )
(6.36)
In this approach, RM(–p2) is initialized (i.e. known) and it is specified as in (6.24) replacing ω2 by –p2.
Once all the residues are computed, by straight forward algebraic manipulations, ZM(p) is generated in its
rational form for the synthesis purpose.
134
6.2.4.3 Actual Design Problem of a Transformer/Filter
From section 6.2.4, the DPA has measured output impedance ~12 Ω, is supposed to drive a RL = 50Ω
load over a finite frequency band of 100MHz to 2.2GHz. As it stands, this problem describes a typical
design of an impedance transformer/filter. In this case, output of the distributed amplifier is considered as
a Thevenin generator EG with internal resistance RG = 12Ω. Referring to above algorithm, we can choose
the impedance normalization number as Ro = 50Ω which makes the normalized load rL = RL/Ro = 1.
Similarly, the normalized generator resistance rG becomes rG = RG/Ro = 12/59 = 0.24.
Actual frequencies may be normalized with respect to upper edge of the frequency passband. Hence, fo is
In
this
case,
normalized
lower
and
upper
edge
selected
as
fo = 2.2 GHz.
angular frequencies become ω1 = 0.0455 and ω2 = 1 respectively. For the construction of the lossless
transformer/filter, a main program on MatLab called “Transfilter.m” 75 . As described in the previous
section, the main program “Transfilter.m” takes all the user defined inputs to minimize the objective
function. Initials for the coefficients can be determined by means of Real Frequency Line Segment
Technique. This is an extra computational step may not be desirable. On the other hand, it is verified that,
ad hoc choice on the initials such as {xi = +1 or -1; i = 1,2,..,n,n+1} are sufficient to end up with a
successful optimization. In fact, this is how we initiated the optimization for the problem under
consideration. “Isqnonlin.m” returns to the main program with optimized polynomial coefficients
{x1, x2,.., xn} = {Ci; i = 1,2,.., n} and xn+1 which in turn yields the normalized value of the series capacitor
Cn+1 = 1/x2n+1 >0. After the optimization, MatLab polynomials a(p) = [a1 a2 a3 an an+1] and
b(p) = [b1 b2 b3 bn bn+1] are determined. Then, ZM(p) = a(p)/b(p) is synthesized and eventually, resulting
transducer power gain in dB and the transformer/filter circuit with optimized element values are printed as
a lossless LC Ladder in unit termination. Let’s review the main program “Transfilter.m” with the following
inputs.
Inputs:
•
Normalized value of rG = 0.24 .
•
Initial values of the polynomial coefficients. It should be noted that, here, we used 5 polynomial
coefficients which will result in a 5-element LC ladder network when ZM(p) is synthesized.
•
Initial value for the series capacitor Cn+1 = 1/x2n+1 = 10 which corresponds to xn+1 = 0.31623
•
Lower edge of the angular frequency band: ω1 = 0.045 which corresponds to 99 MHz to bias the
optimization in favor of f1 = 100MHz. (or normalized frequency = 100MHz/2.2GHz = 0.045455)
•
Upper edge of the angular frequency band: ω2 = 1.
•
Flat gain level of transducer power gain To = 0.99. (Actually, ideal value of To = 1. However, we
prefer to work with To = 0.99 to reduce the gain fluctuations within the passband.)
Results of optimization are given as follows.
•
Optimized unknown vector: x = [2.2069 -0.41107 -7.7351 0.871 3.8151 0.085061] which reveals
optimized coefficients of the auxiliary polynomial C(ω) such that
C = [2.2069 0.41107 7.7351 0.871 3.8151 0.085061]
and xn+1 = 0.085061 meaning that the series capacitor
Cn+1 = 1/(0.085061)2 = 138.21.
•
Coefficients of polynomial of Pn(ω2):
C = [-4.87 -33.9 -75.95 -59.084 -16.29]
Pn(ω2) =( ½)[C2(ω) + C2(-ω)] = B1ω2n + B2ω2(n-1) + … + Bnω2 +1
Analytic-rational form of minimum reactance function ZM(p) = a(p)/b(p):
75
The Matlab program is developed for the research collaboration between Istanbul University (Prof. Dr. Yarman) and Motorola.
135
where,
a(p) as a Matlab polynomial vector: a = [0 1.65 1.0653 2.2253 0.84655 0.45312], and
b(p) as a Matlab polynomial vector: b = [1 0. 0.64563 3.696 2.0286 2.2769 0.45312].
It should be noted that the leading coefficient of a(p) is zero which means that degree of a(p) is one
degree lower than that of b(p) as it should be. Furthermore, a6 = b6 = 0.45312 which yields R1 = 1 as
desired.
•
Synthesis of YM(p) = 1/ZM(p) = b(p)/a(p) by long division yields the following normalized element
values
YM ( p ) = C1 p +
,
1
L2 p +
(6.28)
1
C3 p +
1
L4 p +
1
C5 p + 1
with
C1 = 0.6061; L2 = 0.7029; C3 = 2.870; L4 = 1.165e; C5 = 1.549e; rL = 1.00 The resulting circuit diagram is shown in Fig. 6.46. Actual Capacitors are given by CiA = CiN/2πfoRo;
similarly, actual inductors are given by LiA = LiNRo/2πfo where CiN and LiN represent the normalized values
of capacitors and inductors respectively. Normalization numbers are specified as Ro = 50Ω and
fo = 2.2GHz. Hence we have,
C1A ≅ 0.88 pF; L2A ≅ 2.55 nH; C3A ≅ 4.15 pF; L2A ≅ 4.22 nH; C5A ≅ 2.24 pF; C6A ≅ 200 pH.
Finally, actual termination resistance is rL = 50Ω. Gain performance of the impedance Transformer/Filter,
-0.0432 dB and -2.1454 dB at 2.076GHz and 100 MHz, respectively. Average the gain is given by
Taverage = -1.094 ± 1.0511 dB. The complete gain performance of the impedance transforming filter is
depicted in Figure 6.47.
Figure 6.46: Circuit Topology of transformer/filter with optimized element values
136
Transformer/Filter [T/F] Transducer Power Gain Via RFDCT
0
-1
-2
Gain in dB
-3
-4
-5
-6
-7
-8
-9
-10
0
500
1000
1500
2000
Actual Frequency f (MHz)
2500
3000
Figure 6.47: Optimized transducer power gain of the lossless [transformer/filter] with ideal circuit
components.
6.2.4.4 Measurement Results of a Transformer/Filter
In order to experimentally validate the transformer/filter, prototype board was designed and fabricated. A
photograph of prototype board is included in Figure 6.48. The board size is 36 mm × 11mm. In the above
figure, inductors were realized using high characteristic impedance transmission lines printed on the
board like microstrip lines. The Printed Circuit Board (PCB) is Rogers 4350 with εr = 3.66, the thickness
is h = 0.762 mm. For accurate design, inductors were modeled employing the CST, in which PCB
properties were included. The Q-factor and inductance values of the transmission line were optimized in
CST to end up with flat gain response over the band of interest. Top metal thickness of 2 oz with gold
plating 76 is applied in transmission line for high power handling requirements beyond 30 W.
Figure 6.48: Actual implementation of transformer/filter.
76
Additional plating with gold material is recommended to reduce line losses by Motorola RPRC, FL.
137
The model for the capacitors were received from Modelithics Inc. Careful layout design with practical
considerations was taken into account. Especially, over high frequency operations, diameter size of via
hole and spacing between them require special attention. In the present case, via hole diameter was
taken as 0.15 mm, connecting the component’s grounding from top layer to bottom and separation
between holes was set to 0.3 mm. Adequate numbers of via-holes were placed to provide good electrical
grounding for the shunt capacitors of Fig. 6. Using equivalent models for inductors and capacitors, gain
performance of transformer/filter was simulated on ADS Momentum. The circuit layout was imported from
Cadence. In Figure 6.49, measured and simulated gain performance of transformer/filter is depicted. As
designed, Port 1 is terminated in 12 Ω. Port 2 is connected to 50 Ω. In the course of measurements,
firstly, the scattering parameters of transformer/filter were measured between 50 Ω terminations using
SMA RF connectors. In order to end up with accurate measurement results, each SMA connector is
regarded as a separate two-port.
Insertion loss [dB]
0
-2
-4
-6
-8
-10
0
0.4
0.8
1.2
1.6
2
2.4
2
2.4
Frequency [GHz]
(a)
240
Group Delay [deg]
180
120
60
0
-60
-120
-180
-240
0
0.4
0.8
1.2
1.6
Frequency [GHz]
(b)
Figure 6.49: Simulated (thin line) vs, measured (thicker line) performance of transformer/filter, (a)
insertion loss (b) group delay within operating bandwidth.
138
However, one should bear in mind that the original transformer/filter is driven with RG = 12 Ω instead of
50Ω. Therefore, to end up with the actual performance of transformer/filter as designed, measured
scattering parameters of port 1 must be extracted from the measured S-parameters of the complete
system. Then, the actual scattering parameters are generated with respect to the original input port
normalization number RG = 12 Ω which in turn yields the desired electrical performance of system as it is
driven by the distributed amplifier. In fact, this is what we have done. First, we measured the 50 Ω based
scattering parameters of the SMA connectors used both in Port-1 and Port-2. At this point, measurement
results were compared with those of the model provided with Molex Inc. It has been observed that
measured data shows excellent correlation with the SMA connector model given by Molex (as discussed
in section 4.3.3). Then, the measured S-parameters of the input SMA connector was extracted from the
measured scattering parameters of the two-port, resulting in Ro = 12 Ω based S-parameters.
It should be noted that all the S-parameter measurements were carried out by using HP Network
Analyzer (HP6778). All the above computations were automatically completed on the ADA
CST/Momentum platform, which is interfaced with the network analyzer. Results are plot in Figure 6.49. In
Figure 6.49, the thin line corresponds to the gain performance of Transformer/Filter which is simulated
with the equivalent models of transmission lines inductors and discrete high Q capacitors 77 . Finally, the
thicker line is the measured transducer power gain response in dB of the actual transformer/filter
implemented with transmission line inductors and discrete capacitor. It is seen that the measured gain in
the pass band is about -1.1 dB with about ±0.9 dB fluctuations as expected. Hence, measurements reveal
excellent agreement with simulations.
Furthermore, Figure 6.50 also reveals that, usage of discrete lump inductors (thick line) do not much
change to the gain performance within the passband, however, suppresses the harmonics in the stop
band as they should do. The thick line shows the performance of the simulation obtained with high-Q
discrete inductors from Coilcraft Inc 78 , and for comparison simulated with lumped transmission line as
illustrated by the thin line.
0
Insertion loss [dB]
-10
-20
-30
-40
-50
-60
0
1
2
3
4
5
6
7
8
Frequency [GHz]
Figure 6.50: Simulation performance harmonic filtering up beyond passband. The thick line is
referring with usage of discrete high Q inductors and thin line is for lumped transmission line
77
78
The capacitors are referring to 600S Series Ultra-Low ESR, high Q microwave capacitors, from ATC Inc.
The series of the inductor is 0603CS_XNL (1008HS), from Coilcraft Inc.
139
6.3 Conclusion
Two DPA development for SDR PA applications are demonstrated good results, where the first one has
achieved 10 W output power, 32 dB gain and PAE >15% across the operating bandwidth with cascaded
DPA. The advantages of the proposed technique are explored analytically and large stability margin is
guaranteed with the topology. Good correlation between simulation and measurements is achieved
through a full-wave EM modeling of the complete structure. To the researcher’s knowledge, the best
performance in output power-gain response within an operating bandwidth up to 2 GHz are demonstrated
with low cost implementation technology, and consumes reasonable small size area.
Second DPA development using device load pull impedance termination values to determine vector
combining input and output network design demonstrated highest output power-efficiency in the state-ofart of the DPA results. Theoretical explanation of the proposed technique is given in the chapter.
Measurement results of output power more than 35 W is demonstrated, and with reasonable selection of
impedance values will lead to optimum output power-efficiency performance across bandwidth.
Nevertheless, this DPA exhibited output power and efficiency of 15 W and PAE >15%, respectively
across the bandwidth.
To fulfill the impedance matching to 50 Ω load, with reasonable minimum loss, small area and cost, an
impedance transformer/filter from 12 Ω to 50 Ω is designed. This is the first of its kind. It has been shown
that, RF-DCT reveals an excellent solution to construct an impedance transformer together with a
bandpass filter. The resulting insertion loss performance of transformer/filter which was constructed
employing RF-DCT, was simulated using the lossy models of the lumped components. It has been
exhibited that measured and simulated results are in excellent agreement, and the insertion loss of
1.1±1 dB is recorded experimentally.
140
Chapter 7.
Conclusion and Future Work
7.1 Conclusion
Basic bandwidth limitation analysis of a single ended PA device is discussed. Device selection and circuit
design are essential to achieve broadband frequency response. One should bear in mind that for high
power broadband amplifier requirements, a low-fτ power transistor, and large device periphery must be
considered to achieve output impedance close to 50 Ω. Consequently, stringent input matching is needed
to compensate large Cgs, and this reduces operating gain. However, the gain can be improved with proper
circuit design.
Various broadband design techniques including broadband switched mode PA, linear and efficient PA,
multi-stage PA, and BA are demonstrated. These amplifiers demonstrated state-of-art power performance
of broadband VHF/UHF frequency range. These works give an understanding of power performance over
wide bandwidth, before begin of DA works.
The distributed amplification concept and theoretical analysis of the DA are presented with several
approaches i.e. Beyer, Niclas and McKay model. The Beyer’s method is based on the two-port theory
considers only unilateral small signal transistor model (i.e. Cgd = 0). The Niclas’s method is more general
because there is no simplifying assumption regarding the transistor model, using Y matrix where total
voltages and currents are related. Finally, McKay’s method uses the normalized transmission matrix
approach has the advantage of clearly displaying the traveling wave nature of the DA, even the input and
output lines are constructed with lumped elements. Nevertheless, Beyer’s method still favorable choice to
synthesize DA input/output network to form an estimation gain-bandwidth response in many DA works.
Design methodology of practical DA is presented in this thesis, which provides guidelines to the designers
to realize a DA in an effective time, and without any tedious optimization in board level.
It is important to note that to achieve high DA efficiency performance, the multi current sources must be
combined to a single load by presenting an optimum virtual impedance to each current source in two
directions (Zu(k) and Zr(k)). The generalized design equations are developed. Obviously, to remain R of
50 Ω (and to avoid additional impedance transformation), magnitude and phase properties of the current
source (or transistor) must be adjusted to achieve lower Zu(k). The adjustment can be made according to
designer’s need, complexity of the design circuit, etc. It is still possible to improve efficiency (while
remaining R of 50 Ω) with various ways e.g. non-uniform gate line design, device periphery, etc, which is
an attractive solution for MMIC (monolithic microwave integrated circuit) approach. Nevertheless, Zu(k) can
be reduced further with lower value of R, but as consequence, low insertion loss transformer design must
take places. Measurement results showed PAE > 30% is achieved across the operating frequency range
(10 - 1800 MHz) with a broadband impedance transformer employing parallel coupled line approach. As
an important point, one should note that the design concept presented in this work provides appropriate
guidelines to maximize DA efficiency.
A novel topology of dual fed DA including input and output splitter realized by lumped elements, and with
the termination adjusted for the optimum power performance with low DC supply voltage is presented.
The termination adjustment is accomplished by relevant improvement obtained in comparison to the
conventional DA topology demonstrates the effectiveness of the topology. The output power of ~28 dBm,
covering moderate bandwidth (100-800 MHz), and PAE >20%, and using 7.8 V DC supply voltage is
demonstrated experimentally. The good agreement of the simulations with the realized amplifier
measurement confirms that also in the experimental phase the amplifier is a real improvement to be used
for the wideband frequency band power amplifier with low DC supply voltage.
For a first time, pole-zero identification technique is applied to the DA, to understand the origin of the
oscillation nature due to the multi-loops nature. The analysis considers the DA as a basic feedback
141
oscillator circuit i.e. Hartley Oscillator and using a simplified transistor model. The origin of the oscillation
can be pointed to the trans-conductance nature or multi-loops nature associated due to the feedback
network. Explanation of the odd mode oscillation in DA is given as well. Large-signal stability analysis
based on pole-zero identification is applied to analyze parametric oscillations in high-efficiency DPA. The
parametric oscillation is correlated to a gain expansion phenomenon that directly affects the critical poles
of the circuit. Therefore, design of larger small-signal stability margins is required since those margins
may decrease under large-signal conditions. Large-signal stability analysis is then used to stabilize a
high-efficiency 3-section LDMOS DPA with a minimum impact on circuit performance.
Two DPA development for SDR PA applications are demonstrated good results, where the first one has
achieved 10 W output power, 32 dB gain and PAE >15% across the operating bandwidth with cascaded
DPA. The advantages of the proposed technique are explored analytically and large stability margin is
guaranteed with the topology. Good correlation between simulation and measurements is achieved
through a full-wave EM modeling of the complete structure. To the researcher’s knowledge, the best
performance in output power-gain response within an operating bandwidth up to 2 GHz are demonstrated
with low cost implementation technology, and consumes reasonable small size area.
Second DPA development using device load pull impedance termination values to determine vector
combining input and output network design demonstrated highest output power-efficiency in the state-ofart of the DPA results. Theoretical explanation of the proposed technique is given in the chapter.
Measurement results of output power more than 35 W is demonstrated, and with reasonable selection of
impedance values will lead to optimum output power-efficiency performance across bandwidth.
To fulfill the impedance matching to 50 Ω load, with reasonable minimum loss, small area and cost, an
impedance transformer/filter from 12 Ω to 50 Ω is designed. This is the first of its kind. It has been shown
that, RF-DCT reveals an excellent solution to construct an impedance transformer together with a
bandpass filter. The resulting insertion loss performance of transformer/filter which was constructed
employing RF-DCT, was simulated using the lossy models of the lumped components. It has been
exhibited that measured and simulated results are in excellent agreement, and the insertion loss of
1.1±0.9 dB is recorded experimentally.
7.2 Future Work
7.2.1
Output loading compensation for GaN DPA
Signal losses dominated by the positive FET resistances (i.e. Rgs and Rds) increases proportionally with
bigger device periphery. If these loss mechanisms are somehow mitigated with attenuation
compensation, the gate and drain lines can accommodate additional gate periphery and more sections,
thus, output power can be increased. Cascode is a well known topology for attenuation compensation, as
shown in Figure 7.1. Several works have been reported on high output power and efficiency with cascode
in DA [16], [105], [168]. The motivation of this section is to provide feasible study to achieve high output
power empoying cascode, with combination of vectorially combined current sources while remaining the
load termination close to 50 Ω. Clearly, the proposed topology offers alternative solution (compared to
section 6.2.3) to achieve high output power in DPA solution.
Analytical solution will be discussed, and detail explanation is given how does the loading effect of the
common-source power transistor is resolved when loaded the transistor (e.g. GaN) into the output
transmission line network while preserving current combining to a single load termination (~50 Ω). As a
result, impedance transformation can be eliminated.
A. Theoretical Analysis
Resulting input and output impedance, Zi and Zo, respectively of cascode topology, as shown in
Figure 7.1, is given as
Z i = Rgs1 + jωC gs1 ,
(7.1)
142
Zo =
Rds 2
1 + jωCds 2 Rds 2
[
]
⎡
⎤
Z S 1 + jωC gs 2 Rgs 2
g m2 Z S
,
⎢1 −
⎥+
(
)
1
j
ω
C
R
Z
1
+
jωC gs 2 (Rgs 2 + Z S )
+
+
⎥
gs 2
gs 2
S ⎦
⎣⎢
(7.2)
where ZS is output termination impedance of common-source FET. Note that Cgd is neglected for
simplicity reason.
io
Active load with
common-gate FET
configuration
Vgs2 Cgs2
ir2
ic1
Rgs2
gm2Vgs2
Cds2
Rds2
Zi
Rgs1
Zo
Vds1
−
Yom
ZS
Common-source
+
+
ig2
Input signal
Zo’
gm1Vgs1
Vgs1 Cgs1
ic1
ir1
Cds1
Rds1
−
Vo
Output load
formed by
transmission line
Vds1
-
Figure 7.1: Simplified topology of cascode, where a common-source FET is coupled to the active
load with common-gate configuration.
Input impedance Zi requires similar match as conventional common-source DA. Expanding (7.2), the real
part of Zo can be written as
2
Re{ Z o } =
Rds 2
−
2
1 − ω 2 / ωd
(1 − ω
where ω d = 1 / Rds 2Cds 2 and
2
/ ωd
2
⎛ R +Z S ⎞
⎟ + Z S (ω 2 / ω g 2 )
Z S ⎜ gs 2
⎜
⎟
R
,
g m 2 Rds 2 Z S
gs 2
⎝
⎠
+
2
2
2
⎞
⎛
(
1
−
ω
/
ω
)
g
⎜1 − ω 2 / ω 2 ⎛⎜ R gs 2 + Z S ⎞⎟ ⎟
g ⎜
⎟
⎜
⎟
⎝ R gs 2 ⎠ ⎠
⎝
(7.3)
)
ω g = 1 / Rgs 2C gs 2 . Note that (7.3) derived above is similar as given in [15]. The
term that provides negative resistance from (7.3) is
Z nr = −
g m 2 Rds 2 Z S
(1 − ω
2
/ ωd
2
⎛
⎜1 − ω 2 / ω 2 ⎛⎜ Rgs 2 + Z S
g ⎜
⎜
⎝ Rgs 2
⎝
)
⎞
⎟
⎟
⎠
2
⎞
⎟
⎟
⎠
,
(7.4)
and other terms are passive in nature. The term Znr is directly proportional to gm2 to provide attenuation
compensation positive real part of Zo. For (ω / ωd ) 2 > 1 , one can expect the Znr of (7.4) to become positive
143
which has no benefit in attenuation compensation. Similarly, passive terms of (7.3) can be negative
resistance for (ω / ωd ) 2 > 1 and (ω / ω g ) 2 > 1 causes oscillation. The imaginary part is given below
⎛⎛ R
Im{Z o } =
g m 2 Rds 2 Z S ω / ωd
⎛
⎛
+ ZS
2
2 R
(1 − ω 2 / ωd )⎜1 − ω 2 / ω g ⎜ gs 2
⎜
⎜ R
gs 2
⎝
⎝
2
⎞
+Z S ⎞
⎟ − 1⎟
⎟
Rgs 2 ⎟⎠
⎝⎝
⎠.
2
2
(1 − ω / ω g )
ω / ω g ⎜⎜ ⎜⎜
⎞
⎟
⎟
⎠
2
⎞
⎟
⎟
⎠
+
gs 2
(7.5)
With further simplification of Figure 7.1 for low frequency, analysis is leading to topology given in
Figure 7.2. In general, Z od =
(Ld / Cds 2 )(1 − ω 2 / ωc 2 )
−1
will absorb the effective capacitance (Cds1 and
Cds2) and output line inductance, Ld which synthesized the artificial transmission line.
approximated to 25 Ω at low frequency since both arms are terminated with 50 Ω.
Thus, Zod is
At low frequency (let ω = 0 ), output impedance Z o ' = Rds 2 + Z s (1 − g m 2 Rds 2 ) can be estimated from (7.3).
Output impedance ratio between cascode and common-source configuration given by Zo’/ZS which factor
by (Rds 2 + Z s (1 − g m 2 Rds 2 ) ) / ( g m1 Rds1 ) .
Impedance Z1 seen by current generator gm1 is Z1 // Z om = Rds1 //( Rds 2 + Z od ) /(1 − g m 2 Rds 2 ) . Zom is typically
lower than Rds1, and thus most current gm1Vgs1 flows in the source of upper FET and total
transconductance Gm ≈ gm1. Power delivered by the lower generator is estimated to ( g m1Vgs1 ) 2 Z1 .The
current injection of current generator gm2 depends on the voltage drop across the first generator.
According to power conversion law, power delivered by current generators is equal to power absorbed by
the resistive elements as given below
( g m1Vgs1 ) 2 Z1 + ( g m 2Vgs 2 ) 2 Z 2 = Vds1 / Rds1 + Vds 2 / Rds 2 + Vo / Z od ,
2
2
2
(7.6)
where AV ≈ Vo / Vgs1 can be deduced from (7.6).
Z1
Zs
gm2Vgs2
Zom
io
Zo’
Rds2
gm1Vgs1
+
Vds1
Rds1
−
+
Vds2
+
Zod
Vo
−
−
Figure 7.2: Simplified cascode topology analysis at low frequency.
Let’s considered 2 FETs are identical and having Rdsi = 100 Ω, gmi = 100 mS, and Vgsi = 1 V, where i is
1, 2. From the analysis, Z1 is approximately 11.1 Ω since Zom is 12.5 Ω, output current io ≈ gmVgs1. Hence,
144
current gain Ai ≈1 and voltage gain AV ≈ 22. The output impedance ratio of Zo’/ZS is 2.3 at low frequency.
However, the output impedance at higher frequency range can be maintained as close to 2.3 (at low
frequency) with proper inter-matching design between common-source and common-gate FET. As an
example, an inductor Lp (as shown in Figure 7.5) is introduced for this reason.
B. Design Example
From Figure 7.2, Zod will absorb the effective capacitance of the cascode topology, from (7.5), and output
line inductance, Ld which synthesized the artificial transmission line to form desired ωc. It has been shown
analytically that output impedance of the cascode is ~2 times higher than common-source configuration,
for identical device selection. When the loading effect is resolved, it is beneficial that current combining to
a common load will be achieved without additional transformation network. Figure 7.3 illustrating the
multi-current sources (cascode configuration) are loaded in the output drain transmission line. It is
confirmed experimentally that real part of the output impedance of the die model is very close to the Rds.
Current gain Ai ≈1 indicates that the current contribution is similar as common-source configuration, hence
the biasing condition to common-gate is crucial to deliver similar current injection.
i1(t)
i2(t)
Rds(1)
i3(t)
in(t)
Rds(3)
Rds(2)
Rds(n)
R
i2(t)
i1(t)
Rds(1)
i3(t)
Rds(2)
in(t)
Rds(3)
Rds(n)
Figure 7.3: Current combining to a common node R, with cascode configuration, for n section.
Validation of the concept above for equal magnitude and in-phase combining for n = 3 is selected, leads
to ℜ{Zu(1)} = ℜ{Zu(2)} = ℜ{Zu(3)} = = 150 Ω, and ℜ{Zr(1)} = 150 Ω, ℜ{Zr(2)} = 75 Ω and ℜ{Zr(3)} = 50 Ω, and
imaginary part not exists. For simplicity, a hypothetical drain terminal of a transistor has been modeled as
an ideal current source with parallel resistance (effective real part of cascode) [106], as shown in
Figure 7.4. The imaginary part of Zo (typically capacitance) will be absorbed in Zr(k). An example of output
impedance Zo of cascode GaN die model, showed real part is increased by factor of 2, and imaginary part
reduces by factor of 2. To additively combine the currents at each junction, phase synchronization
between the current source and the transmission line is crucial. Since delays of transmission lines θd(k)
vary linearly with frequency, making the current source delays also vary with frequency would guarantee
delay matching between the sources and the transmission lines. The cascode delivers 2 times higher
power than common-source topology across the frequency, where all the sources are presented with
exactly the required hypothetical optimum impedance of 150 Ω at all frequency.
To verify the design topology with passive elements (e.g. capacitor, etc), and the GaN die model are used
in the HB simulation. First, DC biasing condition is established to satisfy analytical presented in previous
section. Main DC source voltage Vdrain is fed to the cascode, and biasing gate voltage Vg2 of the
common-gate transistor will determine effective Vd2 to allow drain current to flow across the cascode
configuration, as illustrated in Figure 7.5. Applying Kirchoff Law (voltage loop) to the Figure 7.5, DC
biasing can be deduced as
Vg 2 = Vgs 2 + Vd 2 ,
(7.7)
145
where Vgs2 is referring to gate-source of the common-gate transistor. Therefore, the total voltage of Vd1
and Vd2 will determine the Vdrain value. For example, with the GaN die model, Vdrain of 32 V is needed to
generate the similar drain current in cascode configuration, wherelse 28 V for common-source
configuration. As explained in [83], in the absence of Lp, circuit bandwidth is primarily limited by the pole
associated to the internal node of the cascode cells. Therefore, output impedance of cascode especially
at higher frequency operation can be improved with inclusion of Lp.
Zr(2)
Zr(1)
Zr(1)
Zr(1)
Zu(1)
+
v1
-
i1 =I1ej(wt+θ1)
Zr(3)
Zu(2)
+
v2
-
Zr(1)
Zu(3)
+
v3
-
i2 = I2ej(wt+θ2)
+
R vL
i3 = I3ej(wt+θ3)
-
Figure 7.4: Circuit showing multi-current sources to combine at a single load termination,
R = 50 Ω.
Vdrain
+
Vg2
+
Vgs2
-
Vd2
Lp
+
Vg1
Vd1
+
Vgs1
-
-
Figure 7.5: DC biasing condition for cascode topology.
Simulation results of vectorially combined DPA with n = 3 (section), indicated power performance of flat
2 W from DC-7 GHz with cascode topology, and the power is improved by factor of ~1.8 over the
common-source topology, refer to Figure 7.6. Simplified design schematic of cascode with combination of
vectorially combined current sources are presented in Figure 7.7. Since Copt is smaller than Cin 79 , phase
synchronization between gate and drain lines are achieved with capacitively coupled technique [35], and
non-uniform gate line design as shown in [83].
79
Copt is the effective output of CG FET, and Cin is input capacitance of CS FET
146
Output power [W]
2.5
2
1.5
1
0.5
Cascode
Common_source
0
0
2
4
6
8
10
12
Frequency [GHz]
Figure 7.6: Simulated results of power performance between cascode and common-source
topology.
Vdrain
Ld(1)
Ld(3)
Ld(2)
R
Vgb(1)
Q1,(CG)
Vgb(2)
Q2,(CG)
Vgb(3)
Rds(3)
Lp1
Vga(1)
Q1,(CS) Vga(2)
Cga(1)
Lg(1)
Lp2
Q2,(CS) Vga(3)
Lp3
Q3,(CS)
Cga(3)
Cga(2)
Lg(2)
Q3,(CG)
Lg(3)
Lg(4)
Rgt
Figure 7.7: Simplified design schematic of cascode with combination of current combining
approach to a single load termination.
147
Appendix A: Layout Guidelines
A.1 Layer Structures
For digital radio applications, it is recommended to have more layers, typically 6 or 8 layers is required to
adequately shield the noisy lines from the controller. A 8-layers structure which commonly used for the
PCB layout in Motorola is illustrated in Figure A.1.
Top
Inner 1
Inner 2
Inner 3
Inner 4
Inner 5
Inner 6
HDI
Copper
PCB Core
Bottom
Figure A.1: Typical 8-layer structure of PCB.
Layer
Top
Inner 1
Inner 2
Inner 3
Inner 4
Inner 5
Inner 6
Bottom
RF (low
noise
signal)
Solid
ground
plane
Solid
ground
plane
DC
supply
lines
(Vds)
DC supply
Solid
ground
plane
Solid
ground
plane
DC
supply
lines
(Vds and
Vgs)
Lines(Vgs)
Table A.1: Typical signal lines for layer structure.
A.2 Grounding
A ground is usually defined as an equipotential point that serves as a reference potential between two or
more items [Montrose]. For signal referencing ground, the voltage difference typically must be less than a
few milivolts depending on the impedance of the path. Analog ground is isolated from digital or chasis
ground to prevent disruption to sensitive circuits [88]. RF current requires a return path in closed-loop,
and that a good ground improves electrical performance and reduces circuit noise. RF current will always
take the path of least impedance. At low frequencies, where R>>ωL, the current will take the path of least
resistance, as resistance dominates the impedance. At high frequencies, R<<ωL, inductance dominates.
•
Ground Plane
A runner at RF frequency behaves as an inductor. The inductance is a function of the width and length of
the runner. As the width is increased, the inductance will drop. In limit, a ground plane is an infinite width
runner of extremely low inductance at RF frequency. At the RF band, a solid ground plane is essential to
maintain a good RF ground reference for the RF components. Hence the inner 2 and inner 5 are made
into a solid ground plane for low inductance ground reference for the RF components. Long runner has
been avoided from capacitor to ground because the inductance of the long runner can resonate with the
capacitor as shown in Figure A.2.
148
Long runner
Figure A.2: Example of poor grounding.
•
Type of grounding
In RF application, star point grounding as below not encouraged because the RF components can
resonate with the inductance of the long runner connecting the components to the ground plane as shown
in Figure A.3. Parallel connection is an optimal grounding method to improve return path of RF current for
high frequency operation [88], as in Figure A.4. Each subsystem component (1, 2 and 3) will be grounded
to solid grounding material via dedicated hia hole. The via hole can be simply modeled as inductance at
high frequencies, and return current flowing across it has phase delay between voltage reference
potential, and this affect circuit performance. In order to reduce the inductance of the ground via, big and
multiple ground vias, as shown in Figure A.5 is used. Preferred grounding approach in RF is to ground
the components immediately to the ground plane using via is an effective approach.
PA gate
PA drain
Runner
Runner
Solid grounding
Figure A.3: Star point grounding.
1
I1
2
3
I3
I2
Solid grounding
Figure A.4: Parallel connection grounding.
149
PA gate
PA drain
Ground vias
Solid grounding
Figure A.5: Multiple ground vias.
•
Via-holes
Currently, three type of via has been used to connect one section to another, and illustrated in Figure B.6.
They are; normal vias are used to connect runners and components to another section. This runner is
widely used in the RF section. It is through hole via that connects the top and bottom layer section. Buried
vias are used to connect runners within the inner layers. It is not a through hole via. HDI via is a blind via
connecting the HDI layer to the inner 1 or inner 6 layer. This via is connected by buried via to the
subsequent section. The inductance property of this via is unknown. Dimension of vias used in the design
of distributed amplifier is given in Table A.2.
Normal through
hole
HDI Via
Top
Inner 1
Inner 2
Inner 3
Inner 4
Inner 5
Inner 6
HDI
Copper
PCB Core
Bottom
Burried Via
Figure A.6: Via-holes used in two-way radio applications.
Type of vias
Inner diameter (mils)
Outer diameter (mils)
Normal
through hole
12
24
Buried via
8
20
HDI via
6
12
Table A.2: Dimension of via-holes.
150
B.2 PCB routing
•
Routing width
The width of the runner has an impact on the RF characteristics of the runner. The inductance is a
function of the width of the runner. A wide runner has low inductance. The length and the width of the
runner also determine the voltage drop due to the flow of the current through it and dissipation. It is very
essential that the width of the supply line should be high enough to minimize the voltage drop and
dissipation. The width of the runner used in the design is shown in Table A.3.
Type of runner
Recommended minimum width (mils)
RF runners
20
DC supply runners
25
Table A.3: Width of the runners used in the 10 W PA design.
•
Runners routing
The length of the runners is minimized between components to reduce inductance and stray capacitance.
Parallel runners as shown in Figure A.7 (a) have been avoided to reduce coupling effect. Cross runners
are routed perpendicular to each other to minimize magnetic coupling as shown in Figure A.7 (a). A
ground plane below or above the runners will reduce the magnetic coupling of the runners to the
environment by reducing the loop area as shown in Figure A.8. In Figure A.8 (a), magnetic coupling to
environment is significant due to the large loop area. In Figure A.8 (b) ground plane placed underneath of
the runners to minimize magnetic coupling to the external environment. In typical two-way radio design,
inner 1, inner 2, inner 5 and inner 6 is made to be solid ground for this purpose.
Runner
Runner
Runner
Runner
(b)
(a)
Figure A.7: (a) parallel runners (b) perpendicular runners.
151
Runners
Large loop area
(a)
Runners
Loop area
(b)
Figure A.8: Magnetic coupling of the runners (a) larger loop area (b) minimized loop area
A.3 Component Placements in the PCB
•
Inductors
Inductors cannot be placed next to each other. In our design, two inductors in a closed distance placed
perpendicular to each to reduce magnetic coupling, as shown in Figure A.9.
Preferred
Not preferred
(b)
(a)
Figure A.9: Inductor placement to avoid magnetic coupling.
•
RF Bypass Capacitor
RF bypass capacitor is placed as close as possible to the node that requires bypass with short trace, as
highlighted in Figure A.10.
•
Eliminate Stray Capacitance
The capacitance pads can generate unintended stray capacitance due to proximity to the ground plane as
shown in Figure A.11. Shorter distance of the pad to the ground can add significant amount of
capacitance as shown in the formula below. The stray capacitance can be minimized by stripping the
ground underneath of the pad as shown in Figure A.11. In RF/Microwave design, HDI, inner 1 and inner 6
layers are stripped to minimize the stray capacitance.
152
Node to be
bypassed
Node to be
bypassed
Long runner
RF
bypass
RF bypass
(a)
(b)
Figure A.10: (a) Poor placement (b) Good placement.
Capacitor
Pad
Pad
Ground
Figure A.11: Ground underneath component pad has been removed.
153
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Curriculum Vitae
Narendra Kumar received his B.E. (Hons) and M.Sc in Electrical & Electronics Engineering from
University Technology of Malaysia and University Science of Malaysia, respectively, and Dr. -Ing from
RWTH Technical University Aachen, Germany.
He is now with Research & Development of Motorola Technology (M), Penang, Malaysia. He holds 3 US
Patents (and several pending application) and authored more than 30 papers in technical
journals/conferences. He has collaborated with experts in the RF Power Amplifier research area
(including Prof. Dr.–Ing. Rolf Jansen, Dr. Andrei Grebennikov, Prof. Claudio Paoloni, Prof. Ernesto Limiti,
Prof. Juan-Mari Collantes, Prof. Dr.-Ing Georg Boeck, Prof. Arturo Mediano, Mr. Nathan Sokal, Prof.
Vitaliy Zhurbenkho and Prof. Yarman Siddik).
His name was included in the 2009 Who’s Who in Science and Engineering. He was recipient of the
paper award in 2009 IEEE Microwave Propagations and System for his paper on broadband high power
distributed amplifier. He has conducted few IEEE seminars related to switched mode and broadband
amplifier in Malaysia and Thailand Chapter since 2007. Since June 2009, he is serving as Reviewer of
IEEE Transactions on Microwave Theory Techniques, IEEE Transactions Circuit and System,
Electromagnetic PIER journal, etc. His research interest is on high efficiency and broadband power
amplifier, and fast ramping power control.
162