1. Ingeniería

LASCAS 2015 – XXI Iberchip Conference Preliminary Program
Montevideo – Uruguay, 24-7 February 2015
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Day 1 -
LASCAS/Iberchip Program - Tuesday, 24th February 2015
LASCAS/Iberchip Registration
11:00 – 12:00
12:00 – 13:30
Tutorial 2 - Session 1:
Tutorial 1 - Session 1:
Carlos Galup Montoro and Marcio
Cherem Schneider
Subthreshold CMOS design
Time for lunch
13:30 – 14:30
Tutorial 1 - Session 2:
14:30 – 16:00
16:00 - 16:30
Roberto S Murphy
Characterization of
Semiconductor Devices in the
High-Frequency Regime
Carlos Galup Montoro and Marcio
Cherem Schneider
Subthreshold CMOS design
Tutorial 2 - Session 2:
Roberto S Murphy
Characterization of
Semiconductor Devices in the
High-Frequency Regime
Coffee Break / LASCAS/Iberchip Registration
Tutorial 4:
Tutorial 3:
16:30 – 18:00
Manuel Delgado Restituto
Implantable Neural
Recording Interfaces
Gordana Jovanovic, Jose M. de la Rosa,
Gerardo Molina Salgado
Comb-based Decimation
Filters for Sigma-Delta A/D
Converters: Algorithms and
Implementation
17:30 – 18:30
LASCAS/Iberchip Registration
18:30
Welcome Cocktail
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Day 2 -
LASCAS/Iberchip Program - Wednesday, 25th February 2015
8:30 – 9:00
LASCAS/Iberchip Registration
9:00 – 10:40
Opening Ceremony
Keynote – Franco Maloberti,
Data Converters: the road from hundred of MS/s to many GS/s
10:40 – 11:00
Coffee Break
11:00 – 12:40
Session I-A LASCAS
Session I-B LASCAS
Session I-C Iberchip
Analog Circuits I
Digital Filters
CAD
12:40
Lunch
14:00 – 15:10
Industry presentations
Session II-A LASCAS
15:10 – 16:30
16:30 – 17:20
17:20 – 19:00
Imaging
Techniques
Session II-B LASCAS
Session II-C Iberchip
Communication
Systems & Signal
Processing
Embedded Systems
& Computer
Architecture
Coffee break
LASCAS Poster Session I – Iberchip Poster Session I
Session III-A LASCAS
Session III-B LASCAS
Session III-C Iberchip
Data Converters
Test Techniques
Sensors
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Day 3 -
LASCAS/Iberchip Program - Thursday, 26th February 2015
Session IV-B LASCAS
9:00 – 10:40
Digital Signal
Processing
Techniques I
Session IV-A LASCAS
Analog Circuits II
Session IV-C Iberchip
CAD & Digital Design
10:40 – 11:00
Coffee Break
11:00 – 12:40
Panel “Electronic Industry in the Region: Status and
Challenges”
12:40
Lunch
14:00 – 15:00
Keynote – David Atienza
Designing Multi-Parametric Wearable
Monitoring Systems for Scalable Healthcare
Session V-B LASCAS
Session V-A LASCAS
15:00 – 16:20
16:20 – 17:00
17:00 – 18:40
20:30
Pattern Recognition
& Sensing
Digital Signal
Processing
Techniques II
Session V-C Iberchip
Fuzzy Logic & Neural
Networks
Coffee break
Young Professionals/MSc/PhD Students Forum - Poster Session
Session VI-A LASCAS
Session VI-B LASCAS
Session VI-C Iberchip
RF Circuits &
Systems
Digital & ASIC
Design
Signal Processing in
the Digital Domain
Gala Dinner – Club Uruguay
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Day 4 -
LASCAS/Iberchip Program - Friday, 27th February 2015
9:00 – 10:00
10:00 – 10:50
Keynote – Sachin Sapatnekar
Reliability Issues in CMOS, and Spin-Based
Design Beyond CMOS
Coffee break
LASCAS Poster Session II – Iberchip Poster Session II
Session VII-A LASCAS
10:50 – 12:30
Modeling &
Simulation of FET
Devices
Session VII-B LASCAS
FPGA-Based
Applications
Session VII-C Iberchip
Analog & RF
12:30
Lunch
13:50 – 15:00
Embedded Tutorial – Maciej Ogorzalek
3D ICs – Challenges and Advantages
Session VIII-A LASCAS
15:00 – 16:40
Analog & MixedSignal Circuits
Session VIII-B LASCAS
Biomedical &
Neuromorphic
Circuits and Systems
16:40 – 17:00
Coffee break
17:00 – 17:20
Closing Ceremony
Session VIII-C LASCAS
Computing
Techniques
- Keynote Speeches and Tutorials Wednesday 25th February, 9:30 - 10:40
Keynote 1
“Data Converters: the road from hundred of MS/s to many GS/s”
Franco Maloberti
University of Pavia, Pavia, Italy.
Data converters are essential elements for new advanced applications like gigabit Ethernet, optical
communications, radar, set-top box, ultra wide band communications, broadband satellite receivers, and
more. The resultant specifications establish an unprecedented combination of speed, resolution, and power
efficiency. The use of modern nanometer CMOS technologies and digital assisted method are key for
obtaining proper results, especially when the requirement is to operate at conversion speed in the GS/s
range. For those extremely high-speed traditional power-hungry flash architectures have been recently
replaced by time interleaving power effective A/D converters. The preferred single channel schemes are the
SAR or the folding flash architecture.
Therefore, presently, the road from hundred of MS/s to many GS/s ADC starts from high-speed SAR or
equivalent power effective schemes and goes through techniques for making effective the interleaved
architecture. Namely, methods for a suitable clock generation, its distribution and the correction of clock
skew are necessary.
This presentation discusses state-of-the-art silicon implementations of high-speed single channel ADC and
presents analog and digital techniques used to make the interleaved scheme accurate and affordable.
Thursday 26th February, 9:00 - 10:40
Keynote 2
“Designing Multi-Parametric Wearable Monitoring Systems for Scalable Healthcare”
David Atienza
Embedded Systems Laboratory (ESL), EPFL, Switzerland.
Latest progress in microelectronics have enabled the miniaturization of processing elements, radio
transceivers and sensing elements of a large array of physiological phenomena. This situation has made
plausible to realize low cost, low power, miniaturized, yet, smart sensor nodes needed to develop wireless
body-area sensor networks (WBSN). However, the inherent resource-constrained nature of these systems,
coupled with the harsh operating conditions and stringent autonomy requirements, pose important design
challenges to make them provide automated analysis for complex biological signals. This talk discusses the use
of WBSN systems to build scalable healthcare ecosystems. Hence, it addresses system-level design of nextgeneration smart WBSN platforms for personal health monitoring systems, and highlights the unsustainable
energy cost incurred by the relatively straightforward wireless streaming of raw sensor data. To achieve the
extended autonomy required by long-term ambulatory monitoring, this talk advocates for enabling more
embedded intelligence onboard these sensor nodes through a new system-level design approach. This
approach exploits the bio-signals features to apply the new compressive sensing paradigm in the design of
specialized near-threshold computing and memory blocks in order to deploy ultra-low power (ULP) multi-core
processing architectures for automated bio-signals analysis on WBSN. To illustrate the effectiveness of this
approach, this talk focuses on cardiac and multi-parametric monitoring systems and show how it is possible to
achieve wearable ULP electrocardiogram (ECG) arrhythmia detection systems and multi-parametric wellness
monitoring devices that can operate autonomously for long periods of time and support a graceful quality
degradation of the system output based on the available power in the system at each moment in time.
Friday 27th February, 9:00 - 10:00
Keynote 3
“Reliability Issues in CMOS, and Spin-Based Design Beyond CMOS”
Sachin Sapatnekar
University of Minnesota, Minneapolis, USA.
As CMOS technologies have shrunk to the scale of about ten nanometers, reliability and aging problems have
emerged as a major challenge in the design of parts used in the mobile infrastructure, server, and automotive
segments. A true reliability solution must link device models to circuit techniques to architectural
approaches. Current approaches based on projecting device-level models are often pessimistic (in some
cases, by orders of magnitude) because they ignore the inherent resilience of circuits to reliability failures. At
the other end of the spectrum, system-level models often ignore the physics of reliability. This talk will first
discuss research that allows modeling, design, and design automation at various levels to meet in the middle
to solve reliability problems at various levels of design abstraction.
Even with enhanced reliability, further scaling of CMOS circuits is likely to eventually become impractical. In
the final segment of this talk, we will discuss options for a post-CMOS era, with specific focus on spintronics,
an exciting prospect for post-CMOS electronics. This model of computing is based on the use of electron spin
as a state variable, instead of charge as in CMOS, and is based on switching nanomagnets. An overview of
methods for building memory and logic devices using spin-based devices will be provided, with projections for
future research in this area.
Tuesday 24th February, 12:00–13:30 and 14:30-16:00
Tutorial 1
“Subthreshold CMOS design”
Carlos Galup Montoro and Marcio Cherem Schneider
Universidade Federal de Santa Catarina, Florianópolis, Brazil.
The main purpose of this tutorial is the design of integrated circuits for ultra-low-voltage and ultra-low-power
operation. In order to focus on circuit design rather than on the complete MOSFET model, we will emphasize
the subthreshold operation of the MOS transistor. Ultra-low-voltage circuits have gained considerable
attention in recent years because of the emergence of small batteries and self-powered applications. The
main solution to reduce the energy consumption of electronic circuits is to lower the supply voltage.
Theoretically, the minimum supply voltage for a CMOS inverter is 2 (ln2) (kT/q) = 36 mV at room temperature,
as shown by Swanson and Meindl in 1972.
In this tutorial we analyze CMOS logic gates and the Schmitt Trigger circuit in weak inversion operation, and
discuss circuit techniques to approach the theoretical low voltage limit. For analog circuits the minimum
supply voltage is usually considered higher than the minimum necessary for the operation of digital circuits.
Contrary to this common belief, we will show that analog circuits such as rectifiers and oscillators can operate
with supply voltages below (kT/q). In the lecture we will discuss key concepts for ultra-low-voltage operation,
such as MOS transistors with zero or near zero threshold voltage, modeling issues, and ultra-low-voltage
biasing and building blocks. Finally, a section on ultra-low-voltage circuits for energy harvesting is presented.
Tuesday 24th February, 12:00–13:30 and 14:30-16:00
Tutorial 2
“Characterization of Semiconductor Devices in the High-Frequency Regime”
Roberto S Murphy
Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), Tonantzintla, Puebla, México.
The use of semiconductor devices and passive components such as antennas, inductors and transmission lines
is everyday more important in the design and fabrication of integrated circuits for high-frequency
applications. Circuit and system applications employing wireless communications are used nowadays for a
wide variety of applications, and the trend clearly shows that these types of circuits will be needed for a host
of novel applications in the years to come.
This tutorial spans three fundamental aspects of semiconductor and passive devices for high-frequency
applications; their underlying physics, modeling and characterization. During the first part, the particular
structure is analyzed with the aim of identifying the physical mechanisms on which its performance is based,
such as material properties, geometric factors and construction. A second part illustrates the different
methodologies available to relate the physical phenomena to an electric equivalent circuit, addressing the
need for reliable and trustworthy models for the simulation stages of these devices. The final part of the
tutorial focuses on device measurement in the high-frequency regime, covering topics such as calibration
techniques, de-embedding procedures, data transformation and interpretation. The tutorial concludes with
general guidelines for the design and analysis of semiconductor and passive elements, including parasitic
effects which affect the performance of these devices when the operation frequency is in the GHz range.
Tuesday 24th February, 16:30 – 18:00
Tutorial 3
“Implantable Neural Recording Interfaces”
Manuel Delgado Restituto
Instituto de Microelectrónica de Sevilla (Univ. Sevilla - CSIC), Spain
Besides fostering advances in neuroscience, wireless neural prostheses for the measurement of intracranial
neural activity are expected to play a significant role in the development of novel treatments for some
neurological diseases and in the implementation of untethered brain-machine interfaces. As long as these
prostheses are implanted, they have to achieve and maintain stable long-term recordings so that the need for
re-surgery is essentially eliminated. This poses important challenges on the hardware implementation of the
prostheses as they have to exhibit ultra-low power consumption, not only to prevent from harmful effects in
the brain but also to minimize energy requirements; low form factor; versatility, to prove useful in different
scenarios as determined by neurologists; and adaptability to deal not only with the intrinsic statistical
deviations of the fabrication process but also with the non-stationary nature of the electrode-tissue interface.
This tutorial surveys some of the most recent advances in the implementation of wireless neural prostheses
covering different disciplines; since the fabrication of microelectrodes, to the design of communication
protocols, passing though the optimization of ultra-low power analog front-ends and power efficient data
converters. As a demonstration vehicle, an integrated 64-channel neural recording sensor suitable for
acquiring Local Field Potentials (LFPs) and Action Potentials (APs) will be described in detail. In this prototype,
an on-chip dedicated processor defines the operation mode of the channels and implements a full-duplex
protocol for data transmission through a wireless link. In one operation mode, the recording system can be
configured to detect and compress neural spikes so that feature vectors instead of raw signal samples are
transferred. In another mode, the system runs a self-calibration mechanism which automatically adapts the
filter bandwidth and the gain setting of the channels. The sensor also offers different alternatives for raw data
transmission in which the number of active channels and the effective sampling rate are traded-off. In all
cases, the total throughput rate of the sensor keeps below 4Mbps as imposed by the wireless link. The sensor
has been fabricated in a 0.13 µm standard CMOS process and consumes 330 µW from a 1.2 V voltage supply
in the most power demanding mode.
Tuesday 24th February, 16:30 – 18:00
Tutorial 4
“Comb-based Decimation Filters for Sigma-Delta A/D Converters:
Algorithms and Implementation”
Gordana Jovanovic Dolecek(1), Jose M. de la Rosa(2), Gerardo Molina Salgado(1)
(1)Department of Electronics, Institute INAOE, Puebla , Mexico
(2)Instituto de Microelectrónica de Sevilla (Univ. Sevilla - CSIC), Spain.
In oversampled Sigma-Delta analog-digital converters (SD ADC) analog signal is sampled with the frequency
much larger than the Nyquist frequency, which along with the quantization noise shaping, results in an high
resolution compared with the traditional ADCs. This process is done in the modulator, which is the most
critical block of the overall ADC. The sampling rate of the oversampled signal at the output of modulator,
must be decreased to the Nyquist rate (decimated) and the out-of-band components of the quantization
noise must be removed. However, the decreasing of the sampling rate may introduce the aliasing which must
be eliminated in order to prevent the distortion of the oversampled signal. Consequently, the main part of the
decimator is the digital filter, called decimation or antialiasing filter, which has to prevent the aliasing effect.
The decimation is usually performed in different stages. The most critical is the first stage because it works at
high input rate. Due its simplicity, comb filter structures are frequently used at the first stage of decimation.
New demands on SD ADC pose the strong conditions for the comb decimation stage, requiring high
decimation factor, low power and area consumption. Additionally, the magnitude characteristic must have
high alias rejections and a low passband droop to avoid the degradation of the signal after decimation.
In the first part, we will explain the effect of aliasing in the time and frequency domain and we will introduce
comb filter, which is the simplest decimation filter. We will present the advantages and disadvantages of the
comb filter and its two principal structures: recursive and nonrecursive. We will also introduce the polyphase
decomposition, which is useful to move the filtering to lower rate. We will present principal methods for the
improving the magnitude characteristic of the comb filter in the passband, the stopbands, and in both:
passband and stopbands.
In the second part, we will discuss the implementation issue and how to measure the consumed power and
used area in comb-based structure. We will present power efficient and area efficient structures, as well as
the structures with best trade-off between power and area efficiency.
Friday 27th February, 13:50 - 15:00
Embedded Tutorial
“3D ICs – Challenges and Advantages”
Maciej Ogorzalek
Department of Information Technologies, Jagiellonian University, Poland.
The most significant challenge for continued integration of complex systems is energy efficiency. 3D
heterogeneous stacking of diverse circuit blocks is one of the most promising solutions.The tutorial will focus
on three-dimensional integrated circuits (3D lCs) consisting of multiple layers of systems connected vertically.
We will discuss advantages and challenges of current 3D TSV-based technologies and other types of
connections available in news technologies such as carbon nanotubes. One can exploit various options and
choices for silicon and heterogeneous systems. Challenging questions include system types, functionalities,
the variety of materials, TSV-based vertical integration technologies, 3D layout and routing, interconnect
modeling, the system 3D architecture, energy efficiency, technological feasibility, and the multi-objective
optimization. Comparisons between various solutions will be presented and discussed. An overview of
current new concepts for construction of heterogeneous layers on chip containing such devices as energy
scavengers and energy storing devices including hyper-capacitors and micro-batteries will be presented.
Wednesday 25th February
11:00 – 12:40 LASCAS – Session I-A - Analog Circuits I
11:00
ID#96
“High Slew-Rate OTA With Low Quiescent Current Based On Non-Linear Current Mirror”
Pablo Perez, Francisco Veirano, Pablo Castro Lisboa, Fernando Silveira
11:20
ID#79
“Resistorless Switched-Capacitor Current Reference Based on the MOSFET ZTC Condition”
Pedro Toledo, Hamilton Klimach, David Cordova, Sergio Bampi and Eric Fabris
11:40
ID#125
“Design of CMOS Current-mode Multiplier-Divider circuits for type-2 FLC Applications”
Rodrigo B Santos, Paloma Maria Silva Rocha Rizol and Leonardo Mesquita
12:00
ID#158
“A Low-Noise Fully Differential Recycling Folded Cascode Neural Amplifier”
Sammy Cerida, Erick Raygada, Carlos Silva and Manuel Monge
12:20
ID#152
“A Novel and Highly Accurate Bandgap Monitor Circuit for Supply Sequencing”
Ashish Khandelwal, Bharath Kannan and Joseph Khayat
11:00 – 12:40 LASCAS – Session I-B - Digital Filters
11:00
ID#105
11:20
ID#60
11:40
ID#132
12:00
ID#06
12:20
ID#142
“Design of Filterbanks Using a Fast Optimization Approach”
Iman Moazzen and Panajotis Agathoklis
“Signal Enhancement for Gunshot DOA Estimation with Median Filters”
Angelo M. C. R. Borzino, José A. Apolinário Jr., Marcello L. R. de Campos and Luiz W. P.
Biscainho
“A Multi-Standard Interpolation Filter for Motion Compensated Prediction on High
Definition Videos”
Henrique Maich, Guilherme Paim, Vladimir Afonso, Luciano Agostini, Bruno Zatt and Marcelo
Porto
“Realization of 4D Ladder Structured Digital Filters”
George Antoniou and Minas T. Kousoulis
“On simple comb decimation structure based on Chebyshev sharpening”
Miriam Guadalupe Cruz-Jimenez, David Ernesto Troncoso Romero and Gordana Jovanovic
Dolecek
11:00 – 12:40 IBERCHIP – Session I-C - CAD
11:00
ID#46
11:20
ID#49
11:40
ID#03
12:00
ID#22
12:20
ID#51
“Desenvolvimento de uma Ferramenta para a Caracterização Temporal de Portas Lógicas
CMOS”
Ingrid Machado, Paulo Francisco Butzen, Cristina Meinhardt and Eric Fabris
“Uma Abordagem Sistemática para Analisar e Otimizar os Efeitos da Eletromigração nos
Sinais Internos das Células”
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis and Sachin Sapatnekar
“Software Tool for the Analysis of Gate Activation in the ISCAS 85 Combinational Circuits”
Alberto Palacios Pawlovsky
“Uma Arquitetura para Exploração de Paralelismo Multinível utilizando Roteadores
Processantes”
Marcos Cruz, Monica Pereira and Marcio Kreutz
“Synthesis by Optimized Direct Mapping of Extended Burst-Mode gC Finite State
Machines”
Duarte Oliveira, Lester Faria and Leonardo Romano
Wednesday 25th February
15:10 – 16:30 LASCAS – Session II-A - Imaging Techniques
15:10
ID#69
15:30
ID#56
15:50
ID#35
16:10
ID#14
“Resonant Frequency Calculation of Square Diaphragms: A Comparison”
Rayyan Manwar, Livingstone Arjunan, Majid Ahmadi and Sazzadur Chowdhury
“Pathology Grading in Retina Digital Images Using Student-Adjusted Empirical Mode
Decomposition and Power Law Statistics”
Mounir Boukadoum and Salim Lahmiri
“Image Filtering in a CMOS Analog CNN”
Fabian Souza de Andrade, Ygor Oliveira Da Guarda Souza, Edson Pinto Santana and Ana
Isabela Araújo Cunha
“Influence of Cascode and Simple Current Mirrors in Inner Product Implementations for
CMOS Imagers”
Fernanda Oliveira, José Gabriel Gomes and Antonio Petraglia
15:10 – 16:30 LASCAS – Session II-B
Communication Systems & Signal Processing
15:10
ID#91
15:30
ID#30
15:50
ID#145
16:10
ID#116
“Unconventional Signal Processing Architecture for Reconfigurable On-Chip
Communication Systems”
Jose Luis Vazquez, Remberto Sandoval, Blanca Isabel Gea, Ramon Parra and Mario Siller
“Dynamic Resource Allocation in LTE Systems using an Algorithm based on Particle Swarm
Optimization and BetaMWM Network Traffic Modeling”
Flávio H. T. Vieira, Bruno H. P. Gonçalves, Flávio G. C. Rocha, Luan L. Lee and Marcus V. G.
Ferreira
“Optimal location of reclosers in distribution systems considering reliability in
communication channels”
Oscar Danilo Montoya Giraldo, Ricardo A. Hincapié, Mauricio Granada and Andrés Alzate
“A Comparison between RS+TCM and LDPC for G.fast Channel Coding”
Marcos Yuichi Takeda, Fernanda Smith and Aldebaro Klautau
15:10 – 16:30 IBERCHIP – Session II-C
Embedded Systems & Computer Architecture
15:10
ID#32
15:30
ID#48
15:50
ID#17
16:10
ID#44
“Uma Plataforma Multicore Compatível com O Modelo de Programação OpenCL”
Ramon Nepomuceno, Jonatas Santos, Laysson Luz and Ivan Saraiva Silva
“Inferring Custom Architectures from OpenCL”
Krzysztof Kepa, Ritesh Soni and Peter Athanas
“Desarrollo de un prototipo de sistema de cosecha de energía biomecánica aplicado a
estudios neurocientíficos”
Eduardo Queccara and José Alcántara
“Sistema embarcado para detecção de direção rodoviária agressiva”
Juan Diego Diaz Lopez, Mauro Miyashiro and Fabiano Fruett
Wednesday 25th February
16:30 – 17:20 LASCAS Poster Session I
ID#126
ID#72
ID#75
“Dynamically Reconfigurable NoC using a Deadlock-Free Flexible Routing Algorithm with a Low
Hardware Implementation Cost”
Ernesto Cristopher Villegas Castillo, Gabriele Miorandi, Davide Bertozzi and Wang Chau
“Hardware Architecture of the EKF Prediction Stage applied to Mobile Robot Localization”
Luis Federico Contreras Samame, Sérgio Messias Cruz, Carlos Humberto Llanos Quintero and José
Maurício Santos Torres Da Motta
“Area-oriented Iterative Method for Design Space Exploration with High-Level Synthesis”
Jeferson S. Silva and Sergio Bampi
ID#156
“An Analytical Timing-Driven Algorithm for Detailed Placement”
Jucemar Monteiro, Marcelo Johann, José Luis Güntzel and Guilherme Flach
ID#10
“A Basic Method for the Design of an Oscillator using an Electromechanical Resonator”
William Toro, David Altamar, Jorge Martinez and Mauricio Pardo
ID#22
ID#32
ID#112
ID#41
ID#58
“Hardware implementation of a single-cycle one-dimensional median filter”
Alejandro Veiga and Grunfeld Christian
“Advancing in knowledge of the Frobenius Spectrum”
Jonas Augusto Kunzler, Rodrigo Pinto Lemos, Diego Fernando Burgos, Hugo Vinicius Leão E Silva, Yroá
Roblêdo Ferreira, Paulo César Machado and Getúlio Antero de Deus Júnior
“Analysis of two fault locators to different operating states in power distribution system”
Juan David Ramírez Ramírez, Juan José Mora Flórez and Sandra Milena Pérez Londoño
“Reducing the Signal Electromigration Effects on Different Logic Gates by Cell Layout Optimization”
Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis and Sachin S. Sapatnekar
“FPGA Implementation of the CCSDS-123.0-B-1 Lossless Hyperspectral Image Compression
Algorithm Prediction Stage”
Ettore Napoli, Giorgio Lopez and Antonio G.M. Strollo
16:30 – 17:20 IBERCHIP Poster Session I
ID#11
“LM-NoC: Uma Linguagem de Modelagem para Redes em Chip”
Jonathan Wanderley, Ana Luisa Medeiros, Márcio Kreutz and Max Miller Silveira
ID#18
“Paralelismo no Roteamento Global de Circuitos VLSI: Estado da Arte”
Diego Tumelero, Vitor V. Bandeira, Guilherme Bontorin and Ricardo Reis
ID#20
“Multiple bus low power processor design”
Augusto Morita and Wilhelmus Noije
ID#24
ID#27
ID#30
ID#31
“Fuente de alimentación embebida”
Maria Isabel Schiavon, Daniel Alberto Crepaldo, Eduardo Bailón and Carlos Varela
“A Comparison between Direct Digital Measurement Technique and Digital Quadrature
Demodulation for Complex Bioimpedance Measurement Implementation in FPGA”
Allan Oliveira, Raphael Pereira, Joao Dias and Andre Mariano
“Implementação em FPGA de uma FIFO Assíncrona Robusta de Alto Throughput”
Duarte Oliveira, Kledermon Garcia and Roberto D'Amore
“Projeto de um Circuito Integrado para Auxílio ao Controle de Servomotores”
Lucas Garcia and Roberto Neli
Wednesday 25th February
17:20 – 19:00 LASCAS – Session III-A - Data Converters
“An approach to the design of low-jitter differential clock recovery circuits for high
performance ADCs”
Juan Núñez, Antonio J. Ginés, Eduardo J. Peralias and Adoración Rueda
“A Third-Order 1 MHz Continuous-Time Sigma-Delta Modulator in a 130 nm CMOS
Process”
Paulo César C. de Aguirre, Hamilton Klimach and Altamiro Susin
“On the Design of Incremental Data Converters with Extended Range”
Mohammadreza Baghbanmanesh and Franco Maloberti
17:20
ID#47
17:40
ID#86
18:00
ID#50
18:20
ID#113
“MOS-only M-2M DAC for Ultra-Low Voltage Applications”
Israel Sperotto, Hamilton Klimach and Sergio Bampi
18:40
ID#44
“Novel Two-Stage Comb Decimator with Improved Frequency Characteristic”
Gerardo Molina Salgado, Gordana Jovanovic Dolecek and Jose M. De La Rosa
17:20 – 19:00 LASCAS – Session III-B - Test Techniques
17:20
ID#21
17:40
ID#82
18:00
ID#146
18:20
ID#24
18:40
ID#120
“Partial Triplication of a Sparc-V8 Microprocessor Using Fault Injection”
Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida Naviner and Philippe Roche
“On the Functional Test of the Cache Coherency Logic in Multi-core Systems”
Julio Perez Acle, Riccardo Cantoro, Ernesto Sanchez and Matteo Sonza Reorda
“Testing Fully Differential Amplifiers Using Common Mode Feedback Circuit: a case study”
Isis Bender, Guilherme Cardoso, Tiago Balen, Arthur de Oliveira, Lucas Severo and Alessandro
Girardi
“Influence of supplies on fast transient burst test in microcontrollers”
Yann Bacher, Cesar Gori, Nicolas Froidevaux, Henri Braquet, Gilles Jacquemod and Philippe
Dupre
“New Fault Location Method in Power Distribution Systems Using Additional
Measurements”
Juan David Ramírez Ramírez, Juan José Mora Flórez and Cristian David Grajales Espinal
17:20 – 18:40 IBERCHIP – Session III-C - Sensors
17:20
ID#14
17:40
ID#42
18:00
ID#09
18:20
ID#12
“Sistema de control y sensado de policromador MEMS”
Walter Aroztegui, Edgardo Ricci and José Rapallini
“Una plataforma MEMS para la medición IN-SITU y en tiempo real de la tensión/esfuerzo
inducido electroquímicamente en el electrodo de una batería de LITIO-ION”
Sergio Baron
“Optical characterization of uncooled bolometers based on La0.7Sr0.3MnO3 thin films”
Vanuza Nascimento, Bruno Guillet, Shuang Liu, Ammar Arian, Carolina Adamo, Darell
Scholom, Raimundo Freire and Laurence Méchin
“Sensor de Imagen CMOS con Detección de Color Sensible a la Polarización”
José Antonio Rapallini, Jorge Rafael Osio, Mauro Escobar, Ariel Cedola, Cappelletti, Peltzer Y
Blancá, Carbonetto and Lipovetzky
Thursday 26th February
9:00 – 10:40 LASCAS – Session IV-A - Analog Circuits II
9:00
ID#23
“A Computer-Aided Approach for Voltage Reference Circuit Design”
Fabián Olivera and Antonio Petraglia
9:20
ID#81
“A CMOS Low Noise Transconductance Amplifier for 1-6 GHz Bands”
David Cordova, Eric Fabris and Sergio Bampi
9:40
ID#160
10:00
ID#99
10:20
ID#71
“Signal Processing for a Standard Harmonic Analyzer”
Leonardo Trigo and Daniel Slomovitz
“Configurable low noise readout front-end for gaseous detectors in 130nm CMOS
technology”
Hugo Hernandez, Wilhelmus Van Noije and Marcelo Munhoz
“Simulation of MEMS energy harvesting generators based on bennet’s doubler”
Antonio Queiroz and Luiz Oliveira
9:00 – 10:40 LASCAS – Session IV-B - Digital Signal Processing Techniques I
9:00
ID#34
9:20
ID#84
9:40
ID#136
10:00
ID#68
“A Comparative Analysis of Inclusion of PMUs in the Power System State Estimator”
Miguel Yucra, Fabiano Schmidt and Madson Cortês de Almeida
“S-GMOF: A Gradient-based Complexity Reduction Algorithm for Depth-Maps Intra
Prediction on 3D-HEVC”
Gustavo Freitas Sanchez, Mario Saldanha, Bruno Zatt, Marcelo Porto and Luciano Agostini
“Analysis of source separation algorithms in industrial acoustic environments”
Clevis Lozano, Alfonso Chacon, Fernando Merchan and Pedro Julian
“Switched Reluctance Machine Fuzzy Modeling Applied on a MRAC Scheme”
Arnaldo Matute, Julio Viola and Jose Restrepo
9:00 – 10:40 IBERCHIP – Session IV-C - CAD & Digital Design
9:00
ID#28
9:20
ID#29
9:40
ID#10
10:00
ID#52
10:20
ID#25
“LSPart: A Novel Tool for the Decomposition of Low-Power Gated-Clock Finite State
Machines”
Luiz Ferreira, Gabriel Dalalio, Duarte Oliveira and Lester Faria
“An Approach for Design of Asynchronous Systems with Bundled-Data Implementation”
Kledermon Garcia, Duarte Oliveira and Roberto D'Amore
“Estudo e Implementação do Algoritmo Simulated Annealing para Posicionamento de
Células utilizando LabVIEW”
Walter Enrique, Calienes Bartra and Ricardo Reis
“Jezz: An Incremental Legalizer”
Guilherme Flach, Julia Puget, Jucemar Monteiro, Mateus Fogaça, Marcelo Johann, Paulo
Butzen and Ricardo Reis
“Digital IC Design Flow at IC-Brazil Training Program TC1”
Lucas A. de Paris, Pedro Toledo, Jerson P. Guex, Henrique Fellini, Mauro A. Costa Jr., Antonio
Felipe C. de Almeida, Everton Reckziegel, Thiago N. Oliveira and Eric E. Fabris
Thursday 26th February
15:00 – 16:20 LASCAS – Session V-A - Pattern Recognition & Sensing
15:00
ID#53
15:20
ID#140
15:40
ID#133
16:00
ID#19
“Robust smartphone-based human activity recognition using a tri-axial accelerometer”
Cesar Torres Huitzil and Marco Nuno Maganda
“2D Amplitude-Modulation Frequency-Modulation - based Method for Motion
Estimation”
Victor Murray, Paul Rodriguez, Maria Noriega, Alvaro Dasso and Marios Pattichis
“Pattern Recognition Applied to Identification of Chronic Granulocytic Leukemia”
María Del Rocio Ochoa Montiel, Enrique Santamaría-Díaz, Carlos Sánchez-López, Federico
Ramírez-Cruz and Francisco Javier Albores-Velasco
“Motion capture sensor to monitor movement patterns in animal models of disease”
Fabian Hoeflinger, Rui Zhang, Tobias Volk, Enrique Garea-Rodríguez, Adnan Yousaf, Christina
Schlumbohm, Kerstin Krieglstein and Leonhard Reindl
15:00 – 16:20 LASCAS – Session V-B
15:00
ID#118
15:20
ID#144
15:40
ID#155
16:00
ID#05
- Digital Signal Processing Techniques II
“Hardware Design of Fast HEVC 2-D IDCT Targeting Real-Time UHD 4K Applications”
Ruhan Conceição, Ândrio Araújo, Marcelo Porto, Bruno Zatt and Luciano Agostini
“Optimal Location and Sizing of Distributed Generators Using a Hybrid Methodology and
Considering Different Technologies”
Luis F. Grisales, Alejandro Grajales, Oscar D. Montoya, Ricardo A. Hincapié and Mauricio
Granada
“MIL-STD-1553+: Integrated Dual-Redundant Remote Terminal, Bus Controller and Bus
Monitor at 100-Mb/s Data Rate”
Prateek Pendyala
“Black Hole Algorithm for Non-technical Losses Characterization”
Douglas Rodrigues, Caio César Oba Ramos, André Nunes Souza and Joao Paulo Papa
15:00 – 16:20 IBERCHIP – Session V-C - Fuzzy logic & Neural Networks
15:00
ID#01
15:20
ID#40
15:40
ID#57
16:00
ID#08
“Simulation and implementation of controlled chaos and limit cycle oscillatory states, in a
DC motor with a fuzzy logic controller using Concretion based on Boolean Relations”
Andrés Camilo and Barragán Pinzón
“Uso de un Sistema Neurodifuso para la Determinación del Contenido de Grasa en Ratas a
Partir de su Impedancia Bioeléctrica”
Emmanuel Ortega, Jeny Salazar-Anguiano, Esteban Ruíz and David Elías
“Propuesta de una arquitectura para una red neuronal artificial RBF sobre un FPGA”
Niels Prieto Bejar and Carlos Silva Cárdenas
“Implementation of Embedded Systems for Hazardous Locations following Systems
Engineering Methodologies with SysML”
Ricardo Ramirez, Jessie D. Streater, Sharad K. Raj and J. Brent Welch
Thursday 26th February
16:20 – 17:00 Young Professionals/MSc/PhD Students Forum
ID#YP01
“Frame-level Redundancy Correction Technique for SRAM-based FPGAs”
Jorge Tonfat
ID#YP02
“A Study on Buffer Distribution for RRAM-based FPGA Structure Integrated System laboratory”
Somayyeh Rahimian
ID#YP03
“Reliability Evaluation of Combinational Logic Structures”
Eduardo Liebl
ID#YP04
“A Precision Flicker Noise Measurement Setup”
Rafael Puyol
ID#YP05
“Analysis of Optimization Algorithms for Sizing Analog Circuits”
Robson A. Domanski
ID#YP06
“Circuit Design for Sequential Logic Cells Validation”
Helder H. Avelar
ID#YP07
“A Programmable Interface for Extending Android ROM”
Nouha Ghribi
ID#YP08
ID#YP09
ID#YP10
ID#YP11
“Design and digital implementation of the MAC layer of the Bluetooth standard”
Jorge Sanchez-Venegas
“A New Approach for Designing Low Power, Low Noise Multi-GHz Phase Locked Loops in Deep
Sub-μm Digital CMOS”
Susan Schober
“Special Signal Non-Default Routing Rules for Electromigration Improvement”
Lucas de Paris
“HW/SW Co-design of a Reconfigurable NoC for Telecommunication Algorithms”
Blanca Gea
Thursday 26th February
17:00 – 18:40 LASCAS – Session VI-A - RF Circuits & Systems
17:00
ID#16
17:20
ID#40
17:40
ID#151
18:00
ID#38
18:20
ID#70
“A Charge Transfer-Based High Performance, Ultra-Low Power PLL Charge Pump”
Susan Schober and John Choma
“A 0.55-V 1-GHz Frequency Synthesizer PLL for Ultra-Low-Voltage Ultra-Low-Power
Applications”
Omar Abdelfattah, Ishiang Shih, Gordon Roberts and Yi-Chi Shih
“Design Optimization of a CMOS RF Detector”
Nicolas Barabino and Fernando Silveira
“Multimode 2.4 GHz CMOS Power Amplifier with Gain Control for Efficiency Enhancement
at Power Backoff”
Edson Santos, Bernardo Leite and André Mariano
“A Digitally Controlled Oscillator for Fine-Grained Local Clock Generators in GALS MPSoCs”
Guilherme Heck, Leandro Heck, Matheus Moreira, Fernando Moraes and Ney Calazans
17:00 – 18:40 LASCAS – Session VI-B - Digital & ASIC Design
17:00
ID#101
“ASIC Design and Prototyping for Education and Innovation with a Look on Latin America”
Jacobus Swart and Carl Das
17:20
ID#83
“Overhead for Independent Net Approach for Global Routing”
Diego Tumelero, Guilherme Bontorin and Ricardo Reis
17:40
ID#27
18:00
ID#93
18:20
ID#76
“A Design Methodology using Flip-Flops controlled by PVT variation detection”
Alexandro Giron, Victor Avendano and Esteban Martinez
“BAT-Hermes: A Transition-Signaling Bundled-Data NoC Router”
Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes and Ney Laert Vilar
Calazans
“A Fast Pruning Technique for Low-Power Inexact Circuit Design”
Johan Broc, Luca Amaru, Jaume Joven Murillo, Pierre-Emmanuel Gaillardon, Krishna Palem
and Giovanni De Micheli
17:00 – 18:40 IBERCHIP – Session VI-C
Signal Processing in the Digital Domain
17:00
ID#53
17:20
ID#26
17:40
ID#56
18:00
ID#36
18:20
ID#19
“Amplitude-transformed cosine compensator for CIC-based decimation filters”
David Ernesto Troncoso Romero
“Análise da Robustez a Falhas de um Filtro FIR”
Helder Avelar, Denis Franco and Paulo Butzen
“Síntesis e implementación de filtros adaptativos para reducción de ruido en señales de
audio en un sistema embebido basado en arquitectura ARM CORTEX-M4”
Juan Sebastian Rubiano Labrador, Héctor Leonardo Garzón, Jenny Zolanda Castellanos and
Nubia Esperanza Aguilar
“Modelo de referencia de un modulador de la norma DTMB de Televisión Digital”
Reinier Díaz and Ernesto Fontes
“High Performance 2D-DCT Architecture for HEVC Encoder”
Maher Abdelrasoul, Mohammed Sayed, Maha Elsabrouty and Victor Goulart
Friday 27th February
10:00 – 10:50 LASCAS Poster Session II
ID#138
ID#141
ID#119
ID#77
ID#11
ID#65
ID#67
ID#92
ID#97
ID#147
“Automated RDSon Characterization for Power MOSFETS”
Pedro J Escalona Cruz, Manuel A. Jiménez-Cedeño and Rogelio Palomera-García
“Comparison of Alternatives for Voltage Sag Mitigation in Distribution Systems”
Herbert Enrique Rojas, Audrey Soley Cruz and Harvey David Rojas
“Design and construction of a prototype system for gait analysis for research in subjects with
balance problems”
Luis Anza, Enrique Ferreira and Hamlet Suarez
“Estimating SEU Error Rate on Parallel Applications Implemented on Multicore Processors”
Vanessa Vargas, Pablo Ramos, Raoul Velazco, Jean-François Méhaut and Nacer-Edine Zergainoh
“Evaluation of the clustering of video frames using Rank and Histogram methods with Euclidean
and City Block distance measurement for different levels of threshold”
Eddie Galarza, Nicolás Guil and Julián Ramos
“A novel Asynchronous Interface with Pausible Clock for Partitioned Synchronous Modules”
Duarte Oliveira, Tiago Curtinhas, Lester Faria and Leonardo Romano
“Graph - based Cellular Automata with life-like rules: Application to Maximal
Lifetime Coverage Problem in Wireless Sensor Networks”
Antonina Tretyakova
“Modeling the Impact of Heavy Ion on FDSOI NanoCMOS”
Walter Enrique Calienes Bartra, Ricardo Reis and Andrei Vladimirescu
“Real time image compression for eye tracking application”
Frederic Amiel, Barry Boubaccar, Maria Trocan and Marc Swynghedauw
“Design of an IDM-Based Determinant computing unit for a 130nm
low power CMOS ASIC acoustic localization processor”
Roberto Cerdas-Robles, Rodriguez Juan Agustin, Alfonso Chacon and Pedro Julian
10:00 – 10:50 IBERCHIP Poster Session II
ID#33
ID#34
ID#35
ID#39
ID#43
ID#47
“Análise da influência da intensidade das forças de espalhamento no algoritmo SimPL”
Mateus Fogaça, Cristina Meinhardt, Paulo Francisco Butzen and Guilherme Augusto Flach
“Diseño y fabricación nacional de un circuito impreso multicapa con impedancia controlada y
cupón de prueba asociado”
Diego Brengi, David Caruso and Noelia Scotti
“A Terahertz Focal Plane Array for Imaging Applications in 180nm CMOS Technology”
Francisco Brito Filho
“PyHDL - A Cross-compiler from Pure Python to Hardware Description Languages for Modeling and
Simulation of Embedded Systems”
Jaime-Alberto Parra-Plaza
“Implementation a Current Mode Max-Min Circuit in CMOS Technology”
Leonardo Mesquita
“Metodologia gm/ID com Redes Neurais Artificiais para o Projeto de Circuitos Analógicos com
Nanodispositivos”
Tanísia Possani and Alessandro Girardi
Friday 27th February
10:50 – 12:30 LASCAS – Session VII-A - Modeling & Simulation of FET Devices
10:50
ID#55
11:10
ID#157
11:30
ID#104
11:50
ID#29
12:10
ID#07
“Development of a Compact Model for Tunnel FETs Designed for Circuit Simulation”
Matthias Schmidt and Carlos Galup-Montoro
“A Complete Compact Model for Flicker Noise in MOS Transistors”
Alfredo Arnaud and Alain Hoffmann
“Threshold voltage extraction circuit for low voltage CMOS design using basic longchannel MOSFET”
Luis Eduardo Toledo, Pablo Petrashin, Walter José Lancioni and Carlos Daniel Vazquez
“Nanoscale FinFET Global Parameter Extraction for the BSIM-CMG Model”
Alessandra Leonhardt, Luiz Fernando Ferreira and Sergio Bampi
“Techniques for square ELT simulation”
Pablo I. Vaz, Alberto Wiltgen Júnior and Gilson Inácio Wirth
10:50 – 12:30 LASCAS – Session VII-B - FPGA-Based Applications
10:50
ID#134
11:10
ID#08
11:30
ID#49
11:50
ID#33
12:10
ID#149
“Hardware Implementation of a FPGA-based Universal Link for LVDS communications”
Giancarlo Patino, Luis Sanchez, Victor Murray and James Lyke
“An FPGA-Based Time-Domain Frequency Shifter with Application to
LTE and LTE-A Systems”
Felipe Augusto Pereira de Figueiredo, Fabiano S. Mathilde, Fabrício L. Figueiredo and
Fabbryccio A. C. M. Cardoso
“A Study on Buffer Distribution for RRAM-based FPGA Structure”
Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gillardon and Giovanni De Micheli
“Dedicated Hardware for FFT Based Fast Acquisition of GNSS Signals”
Pablo Ezequiel Leibovich, Juan Gabriel Díaz, Javier Gonzalo García and Pedro Agustin
Roncagliolo
“Implementation of a digital integrated circuit for the detection of illegal hunting and
logging”
Carlos Salazar-Garcia, Jordan Montero, Pablo Alvarado-Moya, Rodriguez Juan Agustin and
Alfonso Chacon
10:50 – 12:30 IBERCHIP – Session VII-C - Analog & RF
10:50
ID#58
11:10
ID#02
11:30
ID#21
11:50
ID#23
12:10
ID#50
“Una metodología para el diseño de filtros pasabanda asimétricos de alta Q y orden
fraccional a partir de integradores de orden entero”
Carlos Muñiz-Montero, Luis A Sánchez-Gaspariano, Carlos Sánchez-López
and Alejandro Díaz-Sánchez
“A Dual Reset D Flip-Flop Phase-Frequency Detector for Phase Locked Loops”
Susan Schober and John Choma
“Análise do Impacto da Variabilidade Física nas correntes ION e IOFF
de dispositivos FinFET sub 20nm”
Alexandra Lackmann Zimpeck, Cristina Meinhardt and Ricardo Reis
“Efficient High-Frequency Spin-Torque Oscillators Composed of Two Three-layer MgOMTJs with a Common Free Layer”
Guilherme Flach, Julia Puget, Jucemar Monteiro, Mateus Fogaça, Marcelo Johann, Paulo
Alexander Makarov, Thomas Windbacher, Viktor Sverdlov and Siegfried Selberherr
“A 2.4 GHz Differential Up-Converter Flipped Voltage Follower Harmonic Mixer”
Gregorio Zamora-Mejía, José R. Cano-Martínez, Jaime Martínez-Castillo,
and Alejandro Díaz-Sánchez
Friday 27th February
15:00 – 16:40 LASCAS – Session VIII-A - Analog & Mixed-Signal Circuits
15:00
ID#98
“S-Plane Bode Plots - Identifying Poles and Zeros in a Circuit Transfer Function”
Reza Hashemian
15:20
ID#48
“Design of an Integrated Sampling and Conversion System for Energy Meters”
Evandro Cotrim, Luis Ferreira and Tales Pimenta
15:40
ID#80
16:00
ID#85
16:20
ID#122
“Modeling, Simulation and Experimental Set-Up of a Boost-Flyback Converter”
Frank Florez, Juan Muñoz and Fabiola Angulo
“High Stability Voltage Controlled Current Source for Cervical Cancer Detection using
Electrical Impedance Spectroscopy”
José Alejandro Amaya Palacio and Wilhelmus Van Noije
“Predictive control of a three-phase power converter coupled with LCL filter”
Julio Viola, Jose Restrepo and Flavio Quizhpi
15:00 – 16:40 LASCAS – Session VIII-B
Biomedical & Neuromorphic Circuits and Systems
“A study to implement a Brain-Computer Interface (BCI) based on Sensorimotor Rhythms”
Israel S. Santos and Marilda M. Spindola
“Single Frequency Electrical Impedance Tomography System with
Offline Reconstruction Algorithm”
Leonardo Cechet Moro and Rodrigo Wolff Porto
“An RRAM-Based Oscillatory Neural Network”
Thomas Jackson, Abhishek Sharma, James Bain, Jeffrey Weldon and Lawrence Pileggi
15:00
ID#20
15:20
ID#107
15:40
ID#135
16:00
ID#153
“Step Down DC/DC converter for Micro-Power Medical Applications”
Matias Miguez, Alfredo Arnaud, Alejandro Oliva and Pedro Julian
16:20
ID#154
“A Safe MOSFET Driver for Stimulation of Biological Tissue”
Joel Gak, Alfredo Arnaud and Pablo Mandolesi
15:00 – 16:20 LASCAS – Session VIII-C - Computing Techniques
15:00
ID#62
“Alchemy: An MSP430-based Reconfigurable Processor Architecture”
Caio S. Oliveira and Diógenes C. Da Silva Júnior
15:20
ID#02
“Efficient Emulation of Quantum Circuits on Classical Hardware”
Calebe Conceicao and Ricardo Reis
15:40
ID#90
16:00
ID#25
16:20
ID#159
“Towards reversible QCA computers: reversible gates and ALU”
Jeferson Chaves, Douglas Silva, Victor Camargos and Omar Vilela Neto
“TSV protection: Towards secure 3D-MPSOC”
Martha Johanna Sepulveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet,
Ricardo Pires and Marius Strum
“Multi-hop Collaborative Min-Max Localization”
Alan Sá, Nadia Nedjah and Luiza Mourelle