1. No category

[1]
[4]
[7], [8], [9], [10]
[31]
[25]
[32], [33]
[35],
[37]
[2]
[5]
[18], [19]
[26], [27]
[3]
[6]
[11], [12], [13], [14], [15], [16]
[20], [21], [22], [23], [24]
[28], [29], [30]
[38],
[36]
[39], [40]
National Conference
Intl Conferences
Referred Journals
JCR Journals
Year
2015
2014
2013
2012
2011
2010
2009
2008
2007
2006
2005
2004
2003
Book chapters
Publications by
Miguel Morales Sandoval,
PhD in Computer Science
[17]
[34]
[41],
[42], [43],
[45]
[46], [47],
[49]
References
[1] Miguel Morales-Sandoval and Arturo Diaz-Perez. Scalable GF(p) Montgomery multiplier based on a digit-digit computation approach. IET Computers and Digital Techniques, To appear, 2015.
[2] Miguel Morales Sandoval and Arturo Diaz Perez. Novel algorithms and
hardware architectures for Montgomery multiplication over GF(p). Cryptology ePrint Archive, Report 2015/696, 2015. http://eprint.iacr.org/.
[3] Miguel Morales-Sandoval and Arturo Diaz-Perez. DET-ABE: A Java
API for data confidentiality and fine-grained access control from attribute based encryption. In 9th IFIP WG 11.2 International Conference on Information Security Theory and Practice - WISTP 2015,
pages 104–119, August 2015. doi: 10.1007/978-3-319-24018-3 7. URL
http://dx.doi.org/10.1007/978-3-319-24018-3 7.
[4] R. Garcia, I. Algredo-Badillo, M. Morales-Sandoval, C. Feregrino-Uribe,
and R. Cumplido. A compact FPGA-based processor for the secure hash
algorithm SHA-256. Comput. Electr. Eng., 40(2014):194–202, 2014. ISSN
0045-7906. doi: http://dx.doi.org/10.1016/j.compeleceng.2013.11.014.
[5] Miguel Morales-Sandoval, Ana Karina Vega Castillo, and Arturo DiazPerez. A secure scheme for storage, retrieval, and sharing of digital docu1
[44]
[48]
[50]
ments in cloud computing using attribute-based encryption on mobile devices. Information Security Journal: A Global Perspective, 23(1-2):22–31,
2014.
[6] Mario Muñoz Hernández, Jose Juan Garcia-Hernandez, and Miguel
Morales-Sandoval. Study on the robustness to retyping attacks of fingerprinted digital documents in the frequencial domain. In 9th International
Conference for Internet Technology and Secured Transactions, ICITST2014, pages 1–6, December 2014.
[7] M. Morales-Sandoval,
C. Feregrino-Uribe,
P. Kitsos,
and
R. Cumplido.
Area/performance trade-off analysis of an FPGA
digit-serial GF(2m ) Montgomery multiplier based on LFSR.
Comput. Electr. Eng., 39(2):542–549, 2013.
ISSN 0045-7906.
doi:
http://dx.doi.org/10.1016/j.compeleceng.2012.08.010.
[8] I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, and M. MoralesSandoval.
FPGA-based implementation alternatives for the inner loop of the secure hash algorithm sha-256.
Microprocessors
and Microsystems, 37(6-7):750–757, 2013.
ISSN 0141-9331.
doi:
http://dx.doi.org/10.1016/j.micpro.2012.06.007.
[9] Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, Alicia Morales-Reyes,
Claudia Feregrino-Uribe, Ignacio Algredo-Badillo, Paris Kitsos, and Rene
Cumplido. Karatsuba-Ofman multiplier with integrated modular reduction
for GF(2m ). Advances in Electrical and Computer Engineering, 13(2):3–10,
2013. ISSN 1582-7445. doi: 10.4316/AECE.2013.02001.
[10] Mario Muñoz Hernandez, Jose Juan Garcia-Hernandez, and Miguel
Morales-Sandoval. A collusion resistant fingerprinting system for restricted
distribution of digital documents. PlosOne, 8(12):3–10, 2013. ISSN 19326203.
[11] Ana Karina Vega Castillo, Antonio Cortina Reyes, Miguel Morales Sandoval, and Arturo Dı́az Pérez. A Performance Comparison of Elliptic Curve
Scalar Multiplication Algorithms on Smartphones. In 23rd International
Conference on Electronics, Communications and Computers, CONIELECOMP 2013, pages 114–119, Puebla, Mexico, 2013. IEEE Computer Society.
[12] Miguel Morales-Sandoval and Arturo Diaz-Perez. A compact FPGAbased montgomery multiplier over prime fields.
In Proceedings of
the 23rd ACM international conference on Great lakes symposium on
VLSI, GLSVLSI ’13, pages 245–250, New York, NY, USA, 2013.
ACM. ISBN 978-1-4503-2032-0. doi: 10.1145/2483028.2483102. URL
http://doi.acm.org/10.1145/2483028.2483102.
[13] Miguel Morales-Sandoval and Arturo Diaz-Perez. Area/performance evaluation of digit-digit GF(2k ) multipliers on FPGAs. In Proceedings of the 23rd
2
International Conference on Field Programmable Logic and Applications,
FPL ’13, pages 1–6. IEEE, 2013. ISBN 978-1-4503-2032-0.
[14] Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, and Ignacio Algredo-Badillo. A programmable FPGAbased cryptoprocessor for bilinear pairings over F2m . In Proceedings of
the 8th International Workshop on Reconfigurable Communication-centric
Systems-on-Chip, ReCoSoC 2013, pages 1–8. IEEE, 2013. ISBN 978-14673-6180-4. doi: 10.1109/ReCoSoC.2013.6581528.
[15] Miguel Morales-Sandoval and Arturo Diaz-Perez. Compact FPGA-based
hardware architectures for GF(2m ) multipliers. In Proceedings of the 16th
Euromicro Conference on Digital System Design, DSD 2013, pages 649–
652, Los Alamitos, CA, USA, September 2013. IEEE.
[16] Mario Muñoz Hernández, Jose Juan Garcia-Hernandez, Miguel MoralesSandoval, and Ander Larranga-Cepeda. Study on the impact of fingerprints on the perceptual transparency in digital documents. In Recent
Advances in Information Science, Proceedings of the 4th European Conference of Computer Science, ECCS’13, pages 222–230, October 2013. ISBN
978-960-474-344-5.
[17] Guadalupe de Jesús Morales Bocanegra, Nelson Rangel Valdez, and Miguel
Morales Sandoval. Arquitectura general para la construcción de identificadores de huellas dactilares distribuidos. In Congreso Interdisciplinario de
Cuerpos Académicos, pages 143–157, Guanajuato, Gto., 2013. Universidad
Tecnológica de Guanajuato.
[18] K. Vega-Castillo, A. Cortina-Reyes, and M. Morales-Sandoval. Evaluación
de implementaciones en software de algoritmos para la multiplicación escalar en criptografı́a de curvas elı́pticas. Revista de Ingenierı́a Eléctrica,
Electrónica y Computación, 10(1):22–29, 2012. ISSN 1870 - 9532.
[19] M. Morales-Sandoval and M. A. Nuño-Maganda. Aplicaciones del cómputo
reconfigurable: casos de estudio en criptografı́a y visión por computadora.
Revista Tecnointelecto, 9(1):1–14, 2012. ISSN 1665-983X.
[20] Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino
Uribe, and René Cumplido. Throughput and efficiency analysis of unrolled hardware architectures for the sha-512 hash algorithm. In ISVLSI,
pages 63–68, 2012.
[21] Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil,
Héctor Hugo Avilés-Arriaga, Yahir Hernandez-Mier, and Miguel MoralesSandoval. A hardware architecture for image clustering using spiking neural
networks. In ISVLSI, pages 261–266, 2012.
[22] E. Ruiz-Echartea, M. Morales-Sandoval, M.A. Nuno-Maganda, and
Y. Hernandez-Mier. A Novel Strategy for Image Segmentation of Latent
3
Fingerprints. In 22nd International Conference on Electronics, Communications and Computers, CONIELECOMP 2012, pages 196–201, Puebla,
Mexico, 2012. IEEE Computer Society.
[23] L. Trujillo Vazquez, M. Morales-Sandoval, M. A. Nuno Maganda, and
M. Ruiz Mendez. Elliptic Curve Cryptography on Windows CE devices. In
22nd International Conference on Electronics, Communications and Computers, CONIELECOMP 2012, pages 224–229, Puebla, Mexico, 2012. IEEE
Computer Society.
[24] E. Garcia Amaro, M.A. Nuno-Maganda, and M. Morales-Sandoval. Evaluation of Machine Learning Techniques for Face Detection and Recognition. In 22nd International Conference on Electronics, Communications
and Computers, CONIELECOMP 2012, pages 213–218, Puebla, Mexico,
2012. IEEE Computer Society.
[25] M. Morales-Sandoval, C. Feregrino-Uribe, and P. Kitsos. Bit-Serial and
Digit-Serial GF(2m ) Montgomery Multipliers using Linear Feedback Shift
Registers. IET Computers & Digital Techniques, 5(2):86–94, 2011. ISSN
1751-8601. doi: 10.1049/iet-cdt.2010.0021.
[26] A.L. Trujillo-Vázquez and M. Morales-Sandoval. Algoritmo para la factorización de números compuestos mediante la tangente y el arco-tangente.
Revista Tecnointelecto, 8(1):20–28, 2011. ISSN 1665-983X.
[27] M.E. Ruı́z Echartea, M. Morales-Sandoval, and Y. Hernández Mier. Una
estrategia de segmentacin de imgenes digitales de huellas dactilares latentes.
Revista de Ingenierı́a Eléctrica, Electrónica y Computación, 9(1):1–6, 2011.
ISSN 1870 - 9532.
[28] Miguel Morales-Sandoval, Claudia Feregrino-Uribe, Rene Cumplido, and
Ignacio Algredo-Badillo. A Reconfigurable GF(2m ) Elliptic Curve Cryptographic Coprocessor. In Proccedings of 2011 VII Southern Conference
on Programmable Logic (SPL), pages 209–214, Córdoba, Argentina, 2011.
IEEE Computer Society.
[29] Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, Rene Cumplido, and
Miguel Morales-Sandoval. Novel Hardware Architecture for implementing
the inner loop of the SHA-2 Algorithms. In 14th Euromicro Conference on
Digital System Design (DSD), pages 543–549, Oulu, Finland, 2011. IEEE
Computer Society.
[30] Marco Aurelio Nuno-Maganda, Miguel Morales-Sandoval, and Cesar
Torres-Huitzil. A Hardware Coprocessor integrated with OpenCV for Edge
Detection using Cellular Neural Networks. In 2011 Sixth International Conference on Image and Graphics, pages 957–962, Hefei, China, 2011. IEEE
Computer Society.
4
[31] Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, and
Miguel Morales-Sandoval. Towards a reconfigurable platform to implement
security architectures of wireless communications standards based on the
AES-CCM algorithm. In New Trends in Electrical Engineering, Automatic
Control Computing and Communication Sciences, pages 411–427. Logos
Verlag Berlin, 1 edition, 2010.
[32] M. Morales-Sandoval, C. Feregrino-Uribe, René Cumplido, and I. AlgredoBadillo. A single formula and its implementation in FPGA for elliptic curve
point addition using affine representation. Journal of Circuits, Systems,
and Computers, 19(2):425–433, 2010. DOI: 10.1142/S0218126610006153.
[33] Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido,
and Miguel Morales-Sandoval.
Efficient hardware architecture
for the aes-ccm protocol of the ieee 802.11i standard.
Comput. Electr. Eng., 36(3):565–577, 2010.
ISSN 0045-7906.
doi:
http://dx.doi.org/10.1016/j.compeleceng.2009.12.011.
[34] Marco Aurelio Nuno-Maganda, Cesar Torres-Huitzil, and Miguel MoralesSandoval. Using Handel C for describing picoprocessor architectures. In
Primer Workshop Mexicano de Cómputo reconfigurable y sus aplicaciones
en educación e ingenierı́a, pages 60 – 65, Cancún, Qintana Roo, Mexico,
2010. ISBN 978-607-00-3828-0.
[35] M. Morales-Sandoval, C. Feregrino-Uribe, René Cumplido, and
I. Algredo-Badillo.
An area/performance trade-off analysis of
a GF(2m ) multiplier architecture for elliptic curve cryptography.
Computers and Electrical Engineering, Elsevier, 35(1):54–58, 2009.
doi:10.1016/j.compeleceng.2008.05.008.
[36] Miguel Morales-Sandoval, Claudia Feregrino-Uribe, Rene Cumplido, and
Ignacio Algredo-Badillo. A run time reconfigurable co-processor for
elliptic curve scalar multiplication.
In Mexican International Conference on Computer Science, pages 345–350, Los Alamitos, CA,
USA, 2009. IEEE Computer Society. ISBN 978-0-7695-3882-2. doi:
http://doi.ieeecomputersociety.org/10.1109/ENC.2009.57.
[37] I. Algredo-Badillo, C. Feregrino-Uribe, René Cumplido, and M. MoralesSandoval. Design and implementation of a non-pipelined MD5 hardware
architecture using a new functional description. IEICE Transactions on
Information and Systems, E91-D(10):2519–2523, 2008.
[38] M. Morales-Sandoval, H. M. Marin-Castro, and B. Alemán-Meza. Implementación en hardware reconfigurable de un co-procesador para cálculo
de funciones resumen. TecnoINTELECTO, 5(2):48–57, 2008. ISSN 1665983X.
[39] I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, and M. MoralesSandoval. FPGA implementation cost and performance evaluation of the
5
IEEE 802.16e and IEEE 802.11i security architectures based on AES-CCM.
In 5th International Conference on Electrical Engineering, Computing Science and Automatic Control, pages 304–309. IEEE Computer Society, 2008.
[40] I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, and M. MoralesSandoval. FPGA implementation and performance evaluation of AES-CCM
cores for wireless networks. In 2008 International Conference on ReConFigurable Computing and FPGAs (ReConFig08), pages 421–426. IEEE Computer Society, 2008. doi: 10.1109/ReConFig.2008.54.
[41] R. Duraisamy, Z. Salcic, M. Adriano Strangio, and M. Morales-Sandoval.
Supporting symmetric 128-bit AES in networked embedded systems:
An elliptic curve key establishment protocol-on-chip. EURASIP Journal on Embedded Systems, 2007:Article ID 65751, 9 pages, 2007.
doi:10.1155/2007/65751.
[42] M. Morales-Sandoval and C. Feregrino-Uribe. GF(2m ) arithmetic modules
for elliptic curve cryptography. In 3rd International Conference on ReConFigurable Computing and FPGAs (ReConFig06)., pages 176–183. IEEE
Computer Society, 2006.
[43] R. Duraisamy, Z. Salcic, M. Morales-Sandoval, and C. Feregrino-Uribe. A
fast elliptic curve based key agreement protocol-on-chip (PoC) for securing
networked embedded systems. In 12th IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA
2006), pages 154–161. IEEE Computer Society, 2006.
[44] M. Morales-Sandoval and C. Feregrino-Uribe. Hacia la implementación
y diseño de una arquitectura interoperable para criptografı́a de curvas
elı́pticas. In Séptimo Encuentro de Investigación INAOE, pages 249–252,
2006.
[45] M. Morales-Sandoval and C. Feregrino-Uribe. Hardware architecture for
elliptic curve cryptography and lossless data compression. In 15th International Conference on Electronics, Communications and Computers (CONIELECOM’05), pages 113–118. IEEE Computer Society, 2005.
[46] M. Morales-Sandoval and C. Feregrino-Uribe. On the hardware design of an
elliptic curve cryptosystem. In Fifth Mexican International Conference on
Computer Science (ENC’04), pages 64–70. IEEE Computer Society, 2004.
[47] M. Morales-Sandoval and C. Feregrino-Uribe. On the design and implementation of an FPGA-based lossless data compressor. In International Conference on Reconfigurable Computing and FPGAs (ReConFig’04), pages
29–38. Sociedad Mexicana de Ciencias de la Computación, 2004.
[48] M. Morales-Sandoval and C. Feregrino-Uribe. Implementación hardware
de esquemas de criptografı́a de curvas elı́pticas. In Quinto Encuentro de
Investigación INAOE, pages 249–252, 2004.
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[49] M. Morales-Sandoval, M. Pérez-Gutiérrez, C. Feregrino-Uribe, and
M. Arias-Estrada. Arquitectura hardware de un procesador matricial. In
ENC 2003, IV Congreso Internacional de Ciencias de la Computación.
Avances en Ciencias de la Computación, pages 91 – 96, Apizaco, Tlaxcala,
2003.
[50] M. Morales-Sandoval and C. Feregrino-Uribe. Arquitectura hardware de
un criptosistema de curva elı́ptica con compresión de datos. In Cuarto
Encuentro de Investigación INAOE, pages 209–212, 2003.
7